Thermal-Aware Partitioning and Encoding of Power-Gated FSM

Abstract

Miniaturization and the continued scaling of CMOS technology leads to the high-power dissipation and ever-increasing power densities. One of the major challenges for the designer at all design levels is the temperature management, particularly the local hot spots along with power dissipation. In this work, the controller circuits which are implemented as Finite State Machines (FSMs) are considered for their thermal-aware and power-aware realization. Using Genetic Algorithm (GA), both encoding and bipartitioning of the FSM circuit are implemented to get two subFSMs such that at a particular instant of time, one subFSM is active at a time, whereas the other one is power-gated. Again, thermal-aware realization (in terms of power-density) of this power-gated FSM is done. Therefore, the work concerns with the thermal-aware encoding and partitioning of FSM for its power-gated realization. Average temperature saving obtained in this approach for a set of benchmark circuits over previous works is more than 16%. After getting the final partitioned circuit which is optimized in terms of Area and power-density, thermal analysis of the sunFSMs is performed to get the absolute temperature. As thermal-aware design may increase the area, a suitable area-temperature trade-off is also presented in this paper.