Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization

Yu, Cody Hao; Lung, Chiao-Ling; Ho, Yi-Lun; Hsu, Ruei-Siang; Kwai, Ding-Ming; Chang, Shih-Chieh

doi:10.1109/tcad.2013.2293476

Cited by 14 publications

(8 citation statements)

References 21 publications

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“…In order to obtain the switching probability for each gate in Equation (9), which is necessary to calculate the dynamic power, we implement a 30,000 times logic simulation to generate different input patterns for the circuit and count to the number of switching activities for each gate to obtain the probability. The ILP problems are solved by LINGO 11.0 software [34]. All the experiments are implemented in C++ platform on a DELL T7500 workstation, with Intel Xeon E5620 2.4 GHz (two quad-core processors), 2 GB RAM, and the 64-bit operating system of Windows 7 Enterprise.…”

Section: Experimental Settingmentioning

confidence: 99%

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Sun

Yang

et al. 2017

Algorithms

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As technology scales, negative bias temperature instability (NBTI) becomes one of the primary failure mechanisms for Very Large Scale Integration (VLSI) circuits. Meanwhile, the leakage power increases dramatically as the supply/threshold voltage continues to scale down. These two issues pose severe reliability problems for complementary metal oxide semiconductor (CMOS) devices. Because both the NBTI and leakage are dependent on the input vector of the circuit, we present an input vector control (IVC) method based on a linear programming algorithm, which can co-optimize circuit aging and power dissipation simultaneously. In addition, our proposed IVC method is combined with the supply voltage assignment technique to further reduce delay degradation and leakage power. Experimental results on various circuits show the effectiveness of the proposed combination method.

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Section: Experimental Settingmentioning

confidence: 99%

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Sun

Yang

et al. 2017

Algorithms

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“…Several attempts in the literature have been made to formally address thermal management within task allocation, see, e.g., [1], [2], [14], [19], [20], [21], [29], [30], [31].…”

Section: Related Workmentioning

confidence: 99%

Optimum: Thermal-aware task allocation for heterogeneous many-core devices

Rudi

Bartolini

Lodi

et al. 2014

2014 International Conference on High Performance Computing &Amp; Simulation (HPCS)

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Temperature management is a key challenge for many-core platforms in the dark silicon era as all the cores cannot be powered-on together at the maximum frequency and either some cores should run at lower frequency or only a portion can be used without burning the device. In addition, due to process variations and/or design optimization, not all the integrated processing elements (PEs) are identical and each of them may feature a different power/temperature/frequency trade-off. Many works have been proposed to tackle the thermalaware task mapping problem in multicore devices, but none has yet demonstrated the capability to find optimal solutions within seconds for a large number of cores, with heterogeneous power/frequency operating points, while ensuring a safe transient thermal map. In this paper we propose a new Integer Linear Programming formulation, based on a coarse-grain dynamic thermal model, for this class of problems. Our solver finds optimal solutions in few seconds for a 64 core system. Furthermore, we show that by limiting the number of iterations in the solver, we achieve low optimality gaps, with times compatible to an on-line (execution time) use of the optimal allocator.

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Section: Introductionmentioning

confidence: 99%

“…Different task distributions can result in substantially varied thermal chip profiles [2], so task allocation must consider the spatial thermal correlation of cores, caches, NoC routers and other processor components. A number of popular many-core allocation techniques [2] [3] use objective functions to minimize maximum temperature subject to constraints to meet physical design limits. Since it is computationally expensive in such systems to model the thermal behavior of all system components, in general, existing allocators do not consider many-core router temperatures or the thermal impact of earlier allocation decisions while performing task assignment.…”

Section: Introductionmentioning

confidence: 99%

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Reinforcement Learning for Thermal-aware Many-core Task Allocation

Tessier

Burleson

2015

Proceedings of the 25th Edition on Great Lakes Symposium on VLSI

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To maintain reliable operation, task allocation for manycore processors must consider the heat interaction of processor cores and network-on-chip routers in performing task assignment. Our approach employs reinforcement learning, a machine learning algorithm that performs task allocation based on current core and router temperatures and a prediction of which assignment will minimize maximum temperature in the future. The algorithm updates prediction models after each allocation based on feedback regarding the accuracy of previous predictions. Our new algorithm is verified via detailed many-core simulation which includes on-chip routing. Our results show that the proposed technique is fast (scheduling performed in < 1 ms) and can efficiently reduce peak temperature by up to 8 o C in a 49-core processor (4.3 o C on average) versus a competing task allocation approach for a series of SPLASH-2 benchmarks.

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Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization

Cited by 14 publications

References 21 publications

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

NBTI and Power Reduction Using an Input Vector Control and Supply Voltage Assignment Method

Optimum: Thermal-aware task allocation for heterogeneous many-core devices

Reinforcement Learning for Thermal-aware Many-core Task Allocation

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