Theory of the fully depleted SOS/MOS transistor

Worley, E.

doi:10.1016/0038-1101(80)90020-9

Cited by 29 publications

(3 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…It is observed that Vth in the (111) GOI nMOSFETs significantly increases with thinner TGOI. This increase in Vth can be explained by a high level of the back interface state density [29,30]. The change in back surface potential is larger in thinner GOI MOSFETs.…”

Section: Resultsmentioning

confidence: 96%

Electrical Properties of Ultra-Thin Body (111) Ge-On-Insulator n-Channel MOSFETs Fabricated by Smart-Cut Process

Lim

Zhao

Sumita

et al. 2021

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

We have systematically examined electrical characteristics of ultra-thin body (UTB) (111) Ge-on-insulator (GOI) n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) fabricated by the smart-cut process and have compared their electrical properties with those of (100) ones. The (111) GOI thickness was varied from 29.4 to 7.3 nm. The normal MOSFET operation of a 7.3 nm-thick (111)-oriented GOI nMOSFET has been demonstrated with a reasonable ON/OFF ratio of 10 4 . However, degradation in the effective electron mobility and subthreshold swing (SS) of the (111) GOI nMOSFETs with decreasing the GOI thickness (TGOI) was observed. Raman analyses and electrical characteristics of GOI nMOSFET under back-gate operation has suggested that a high interface state density at (111) GOI/buried oxide interfaces as well as low GOI film quality near the back interfaces can be an origin of this degradation of the electrical properties with thin body channels.Index Terms-Ge-on-insulator (GOI), smart-cut technology, (111) surface orientation, MOSFETs, ultra-thin body (UTB) I. INTRODUCTIONS conventional Si-based complementary metal-oxidesemiconductor (CMOS) devices have encountered with physical limitations of scaling down, Ge has been studied as an alternative channel material due to its high carrier mobility and compatibility with the conventional Si CMOS technology [1][2][3]. In scaling down Ge MOS devices, an ultra-thin body (UTB) GOI structure is essential for strong immunity against shortchannel effects [4][5][6]. Recently, GOI MOSFETs, which can be realized under low thermal budget, have become more attractive because of the applicability to 3-dimensional stacked CMOS, promising as a future CMOS platform [7,8]. Here, the further improvement in electrical characteristics of n-channel GOI MOSFETs is one of the main challenges in developing the GOI CMOS. Thus, technology boosters to realize highperformance UTB GOI nMOSFETs is strongly needed.In order to enhance the GOI nMOSFET performance, the surface orientation must be carefully taken into account because of the anisotropic carrier transport properties of Ge [9]. Here, the (111) surface orientation of Ge has lower effective mass Manuscript received February xx, 2021.

show abstract

Section: Resultsmentioning

confidence: 96%

Electrical Properties of Ultra-Thin Body (111) Ge-On-Insulator n-Channel MOSFETs Fabricated by Smart-Cut Process

Lim

Zhao

Sumita

et al. 2021

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

show abstract

“…le dopage ou le profil de dopage, -la densité de charges fixes aux deux interfaces, -la densité d'états de surface (uniformément distribués) à l'interface arrière (avec des états de type accepteur entre la bande de conduction et le milieu de la bande interdite, et des états de type donneur entre la bande de valence et le milieu de la bande interdite). Cette distribution a été choisie en accord avec [4,5], -les tensions de grilles avant et arrière appliquées par rapport à la source, -les épaisseurs de la silice, du silicium et de l'isolant arrière.…”

Section: Programme De Simulationunclassified

“…En effet, bien que plusieurs auteurs [1][2][3][4][5][6] se soient attachés à donner une expression de la tension de seuil avant de ces structures dans diverses situations, aucune analyse détaillée de l'influence de l'interface arrière sur le fonctionnement de ces dispositifs n'existe à notre connaissance.…”

Section: Introductionunclassified

Simulation d'un transistor MOS silicium-sur-isolant à désertion profonde avec contrôle du potentiel arrière

Brini¹

1984

Rev. Phys. Appl. (Paris)

View full text Add to dashboard Cite

2014 Nous considérons les structures MOSFET/SSI (silicium-sur-isolant) de types N et P contrôlées par deux grilles. Dans le cas d'une couche mince de silicium peu dopé, les deux interfaces du transistor MOS sont fortement couplées. Pour étudier l'action des paramètres d'interface sur les tensions de seuil, nous avons réalisé une intégration numérique de l'équation de Poisson. Nous obtenons le profil de potentiel et les densités d'électrons et de trous correspondantes en fonction des tensions de grilles avant (Vg1) et arrière (Vg2) appliquées. Nous déduisons aussi les caractéristiques Id(Vg1, Vg2) à faible tension de drain. Les caractéristiques Id(Vg2) simulées sont comparées aux caractéristiques Id(Vg2) obtenues avec des transistors CMOS/SOS. Le saphir de ces dispositifs a été localement aminci pour contrôler le potentiel de surface arrière à l'aide d'une grille arrière. Cette comparaison nous fournit des mesures directes de la densité d'états rapides et de la charge fixe à l'interface arrière. Abstract. 2014 We consider SOI MOSFET structures of N and P type controlled by two gates. In the case of a lightly doped thin film silicon, the two interfaces of MOS transistor are strongly coupled. In order to study the action of the interface parameters on the threshold voltages, we carried out a numerical integration of Poisson's equation. We obtain the potential profile and the corresponding electron and hole densities, as a function of the applied front

show abstract

SOI CMOS Devices—Basic

Kuo

1998

CMOS VLSI Engineering

View full text Add to dashboard Cite

Theory of the fully depleted SOS/MOS transistor

Cited by 29 publications

References 11 publications

Electrical Properties of Ultra-Thin Body (111) Ge-On-Insulator n-Channel MOSFETs Fabricated by Smart-Cut Process

Electrical Properties of Ultra-Thin Body (111) Ge-On-Insulator n-Channel MOSFETs Fabricated by Smart-Cut Process

Simulation d'un transistor MOS silicium-sur-isolant à désertion profonde avec contrôle du potentiel arrière

SOI CMOS Devices—Basic

Contact Info

Product

Resources

About