Theoretical Study of Self-Heating-Induced Thermal Stress Effects on Quantum Transport in p-Type Ultrathin Body-FinFET by Multiphysics Simulation

The rising temperature due to a self-heating or thermal environment not only degrades the subthreshold performance but also intensifies thermal stress, posing a severe challenge to device performance and reliability design. The thermal stress effects on the ON-state performance of the p-type fin field-effect transistor were previously studied. However, as far as we know, how thermal stress affects its subthreshold conduction remains unclear, which is studied in this manuscript. The impact of thermal stress due to the self-heating of adjacent devices on subthreshold conduction is investigated by solving the quantum transport, thermal conduction, and force balance equations for ballistic transport and dissipative transport with phonon scattering. Then, the thermal stress effects at different ambient temperatures are further discussed and analyzed. The simulation results show that the OFF-state leakage current can be reduced by thermal stress, even up to 9.28% for the (110)/[001] device operating at an ambient temperature of 550 K, and its reduction is the comprehensive result of the thermal stress effects on the band structure, potential profile, carrier distribution, and source-to-drain tunneling. In addition, the thermal stress has no significant effects on subthreshold swing although it can change the magnitude of the subthreshold current. Moreover, the effect of thermal stress on subthreshold conduction is highly dependent on the thermal environment of the device and the crystal orientation of the channel semiconductor material.

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Theoretical Study of Self-Heating-Induced Thermal Stress Effects on Quantum Transport in p-Type Ultrathin Body-FinFET by Multiphysics Simulation

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Multiphysics simulation study of thermal stress effects in nanoscale FinFETs heterogeneously integrated with GaN high-power device on silicon substrate

Multiphysics simulation study of thermal stress effects in nanoscale FinFETs heterogeneously integrated with GaN high-power device on silicon substrate

Investigation of thermal stress effects on subthreshold conduction in nanoscale p-FinFET from Multiphysics perspective

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