Theoretical limits for signal reflections due to inductance for on-chip interconnections

Abstract

Transmission line properties of on-chip wiring need to be taken into account due to the great lengths and fast rise times encountered. As the line lengths and circuit speeds increase, the wavelength decreases, and the distributed n-section RC representation will be no longer adequate to analyse signal integrity. With these trends it is becoming more important to include inductance when modeling on-chip interconnect. The electrical phenomena that have to be investigated are governed by the electromagnetic theory.We present first in this paper an efficient and accurate modeling and simulation technique of frequency-dependent transmission lines to determine interconnection characteristics. The electromagnetic approach is then used to determine the limits where effects such as signal reflections can be predicted. The theoretical limits calculated are then illustrated.

Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach

“…Most existing crosstalk models and reducing techniques consider only capacitive coupling [2][3][4][5][6]. However, at high operating frequencies, inductive-crosstalk effects can be substantial and should be included for complete coupling-noise analysis.…”

“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. crosstalk [1][2][3][4] that are based on Elmore delay model [5]. Techniques for crosstalk and delay minimization under the lossy transmission line model have also been studied extensively in the literature [6][7][8][9][10].…”