Theoretical Investigation of Dual Material Junctionless Double Gate Transistor for Analog and Digital Performance

Abstract

In this paper, we report the 2-D drain current model for asymmetric dual material (DM) junctionless double gate transistor. On the basis of channel potential, transconductance and its higher order derivatives are estimated and verified with the ATLAS 3-D device simulator results. The developed model is also applicable to investigate the digital performance of the device in terms of voltage transfer characteristics of nMOS inverter circuit. The impact of the length of control gate on the analog performance has also been investigated. Results also highlight the advantage of DM gate over the single material gate for digital and analog applications using CMOS inverter and common source amplifier through exhaustive circuit simulation.

Analytical current Model for Dual Material Double Gate Junctionless Transistor

“…It has been observed that on current of proposed device is maximum and off current is minimum (1pA at channel length 120nm) which means that Ion/Ioff ratio improves compares to single material double gate junctionless transistor. Subthreshold slope of our device is minimum compare to [11] dual material double gate junctionless transistor. Threshold voltage of my proposed device and other researcher's device mentined in references is approximately same [21] [22].…”

“…But, bulk current model for dual material double gate junctionless transistor was not found in literature. Vandana Kumari et.al demonstrated drain current model for dual material double gate junctionless transistor, but the model failed to mention the effect of channel thickness, gate oxide thickness, channel doping density and channel length on drain current [11]. In [12] current model of subthreshold region was not mentioned.…”

A Novel Approach to Model Threshold Voltage and Subthreshold Current of Graded-Doped Junctionless-Gate-All-Around (GD-JL-GAA) MOSFETs

“…The calculation of subthreshold current based on minimum channel potential (similar from [26]) can be evaluated by using the drift-diffusion equation as: This plot reflects that the IOFF significantly decreased when the channel length is increased from 20nm to 40nm. It occurred due to the barrier height being raised between the source and channel.…”

An Approach for Drain Current Modeling Including Quantum Mechanical Effects for a DMDG Junctionless Field Effect Nanowire Transistor

“…Baruah et al [13] presented a study on analog circuit performance of a DMDG-JLFET with a high k-spacer. Recently, Kumari et al [10] proposed a theoretical investigation of DMDG-JLFET for analog and digital performance. Gupta et al [14], showed that a continuous increase in the threshold voltage was observed as we move down towards sub 10nm regime of the silicon film thickness.…”