Theoretical and Experimental Study of High-Energy Implanted Collectors for Bipolar Transistors in Bipolar-Complementary Metal Oxide Semiconductor Transistor Technology

Abstract

This work is a theoretical and experimental study of the properties of retrograde collector profiles for bipolar transistors produced using high-energy ion implantation. One-dimensional device simulations are carried out, and show that compared with a uniform profile, the retrograde profile allows transistor operation at higher current levels without incurring an unacceptable increase in the base-collector capacitance. Two-dimensional process and device simulations are also carried out to analyze the two-dimensional electrical behavior of the retrograde collector. At low collector-emitter bias, quasi saturation is observed due to the vertical drop in potential, which is associated with a lateral drop in the potential in the collector resistance, and must be minimized. At high collector-emitter bias, the injection regime, resulting from the Kirk effect, occurs. Experimental bipolar transistors are designed and fabricated based on these simulation results. The proposed self-aligned design minimizes both the extrinsic base-collector junction capacitance and the series collector resistance. A measured transit frequency (f T) of 7.8 GHz is obtained, which is ample for many analog and digital VLSI circuits which require operating frequencies up to a few gigahertz.

Interface Characteristics of SiO[sub 2]/Si Structure with High Energy Boron Implantation

“…The implantation energy was constant at 0.8 MeV. In these profiles, the concentration peaks have values between 2.6 ϫ 10 16 to 2.7 ϫ 10 17 /cm 3 . The carrier concentration of a Si substrate is also shown in this figure and decreased at the SiO 2 and Si interface due to the segregation effect by oxidation.…”

“…[1][2][3][4][5] It can provide a technique to form a buried layer, a retrograde well, and proximity gettering. 2 Particularly, latch-up susceptibility of complementary metal oxide semiconductor ͑CMOS͒ circuits can be improved.…”

“…High energy ion implantation into silicon is used in ultralargescale integration ͑ULSI͒ fabrication processes because it can be used to control electrical properties in layers within a few micrometers from the surface. [1][2][3][4][5] It can provide a technique to form a buried layer, a retrograde well, and proximity gettering. 2 Particularly, latch-up susceptibility of complementary metal oxide semiconductor ͑CMOS͒ circuits can be improved.…”

“…1 Recently, multiple high energy ion implantations were used to generate profiled wells. 3 By employing multiple, high energy ion implantations, a profiled well can easily be implemented in a high performance CMOS. Otherwise, high energy ion implantation causes severe damage to the crystalline lattice.…”