Theorem proving guided development of formal assertions in a resource-constrained scheduler for high-level synthesis

Narasimhan, N.; Teica, E.; Radhakrishnan, R.; Govindarajan, Sriram; Vemuri, Ranga

doi:10.1109/iccd.1998.727079

Cited by 13 publications

(12 citation statements)

References 18 publications

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“…Our work is related to translation validation [19], [33], [42], [46], [47], [53], [54], relational approaches to reasoning about programs [5], [7], [15], [28], [35], CSP refinement checking [13], [27], [39], [51], and HLS verification [2], [14], [31], [34], [41]. We now discuss each area in more detail.…”

Section: Related Workmentioning

confidence: 99%

“…Techniques like correctness-preserving transformations [14], formal assertions [41], symbolic simulation [3], and relational approaches for functional equivalence of finite state machines with datapaths [29]- [32] have been used to validate the scheduling step of HLS. In contrast to these approaches our algorithm can handle most of the transformations currently being used for HLS in an uniform and modular framework.…”

Section: Hls Verificationmentioning

confidence: 99%

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Translation Validation of High-Level Synthesis

Kundu

Lerner

Gupta

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The growing complexity of systems and their implementation into silicon encourages designers to look for ways to model designs at higher levels of abstraction and then incrementally build portions of these designs-automatically or manually-from these high-level specifications. Unfortunately, this translation process itself can be buggy, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. Therefore, checking if the implementation is a refinement or equivalent to its initial specification is of tremendous value. In this paper, we present an approach to automatically validate the implementation against its initial high-level specification using insights from translation validation, automated theorem proving, and relational approaches to reasoning about programs. In our experiments, we first focus on concurrent systems modeled as communicating sequential processes and show that their refinements can be validated using our approach. Next, we have applied our validation approach to a realistic scenario-a parallelizing high-level synthesis framework called Spark. We present the details of our algorithm and experimental results.

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Section: Related Workmentioning

confidence: 99%

Section: Hls Verificationmentioning

confidence: 99%

Translation Validation of High-Level Synthesis

Kundu

Lerner

Gupta

2010

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Moreover, the model must be sufficiently small. Narasimhan et al [17] applies theorem proving to verify the correctness of the FDLS scheduling strategy. Our approach is distinct from these by following the "refinement method" where we reason with a simpler model and verify that a more efficient strategy refines it.…”

Section: Figure 4 Tla Proof Rulesmentioning

confidence: 99%

Formal verification of concurrent scheduling strategies using TLA

Grov

Michaelson

Ireland

2007

2007 International Conference on Parallel and Distributed Systems

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There is a high demand for correctness for safety critical systems, often requiring the use of formal verification. Simple, well-understood scheduling strategies ease verification but are often very inefficient. In contrast, efficient concurrent schedulers are often complex and hard to reason about. This paper will show how the TLA logic can be used to verify schedulers of concurrent components. TLA allows us to prove that one program preserves the behaviour of another program, in particular that an efficient scheduling strategy preserves the behaviour of a simpler one. For an arbitrary program we can use the simpler scheduler for correctness verification, knowing that the properties also hold in the more efficient one, which we then implement. This approach is illustrated with the Hume programming language, which is based on concurrent rich automata. We show an efficient extension to the Hume scheduler, and prove that this extension preserves the behaviour of the standard Hume scheduler.

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“…Related work: According to [12], synthesis-verification maybe divided into pre-synthesis verification of synthesisalgorithms (e.g., [14]), formal synthesis where the constructive steps are embedded into a theorem prover (e.g., [3]), and post-synthesis verification where the synthesized results are verified afterwards (e.g., [13]). While most methods of post-synthesis verification use theorem proving techniques, a graph-based method was proposed in [8].…”

Section: Introductionmentioning

confidence: 99%