The VMP network adapter board (NAB): high-performance network communication for multiprocessors

KanakiaH.,; CheritonD.,

doi:10.1145/52325.52343

Cited by 69 publications

(18 citation statements)

References 7 publications

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“…The topic was particularly popular in the early 1990s [4,5,6,8,12,15,26,32], but attempts to commercialise the technology, such as the Virtual Interface Architecture [3], based upon the Cornell U-Net project [32] were mostly unsuccessful. After a period of relative quiet, there appears to be a resurgence in interest in the area, perhaps spurred by the beginnings of commercial adoption of advanced NIC designs.…”

Section: Related Workmentioning

confidence: 99%

An operating system architecture for network processors

Muir

Smith

2005

Proceedings of the 2005 ACM Symposium on Architecture for Networking and Communications Systems

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Network devices have become significantly more complex in recent years, with the most sophisticated current devices incorporating one or more general-purpose CPUs as part of their hardware. The need for such processing capability is motivated by the desire to move greater amounts of functionality, of ever-increasing complexity, from the host CPU to the network device itself. A significant challenge in doing so is managing the complexity of the software running on the network device.We believe that the complexity of this software has reached the point where it is now on a par with many generalpurpose systems, and thus requires the same management infrastructure-an operating system for network processors.In this paper we describe an architecture for such an OS, presenting the features most relevant to network processors and describing similarities to and differences from a generalpurpose OS. We present a prototype implementation using an SMP system as a virtual network processor, and show how our prototype was used to evaluate a novel user-space interface to a network device.

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Section: Related Workmentioning

confidence: 99%

An operating system architecture for network processors

Muir

Smith

2005

Proceedings of the 2005 ACM Symposium on Architecture for Networking and Communications Systems

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“…Implementations include the XTP Protocol Engine [8], the Nectar communications processor [14], and the VMP adaptor [23]. Follow on work [22,33] based on the Protocol Engine architecture implemented TCP/IP on the host interface for a 622Mb/s ATM network.…”

Section: Introductionmentioning

confidence: 99%

10Gb/s Ethernet performance and retrospective

Pope¹,

Riddoch²

2007

SIGCOMM Comput. Commun. Rev.

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This paper presents both a retrospective of the development of network interface architecture, and performance and conformance data from a range of contemporary devices sporting various performance enhancing technologies. The data shows that 10Gb/s networking is now possible without statefull offload and while consuming less than one CPU core on a contemporary commodity server. INTRODUCTIONFrom ARPANET [6] and Ethernet [30] [33,21]. These developments to the mid90s have come to represent the roots of today's main-stream LAN interface designs. However, while is the case that offloads are now regarded as commodity items, the desirability and utility of even the most simple offload should remain under debate. For example Stone and Partridge [35] describe a study of the root cause of network errors which escape the Ethernet FCS check and find many systematic errors in hardware and software.One architecture which received attention from the late80s was that of executing the transport protocol on the host network interface. Implementations include the XTP Protocol Engine [8], the Nectar communications processor [14], and the VMP adaptor [23]. Follow on work [22,33] based on the Protocol Engine architecture implemented TCP/IP on the host interface for a 622Mb/s ATM network. This TCP/IP offload architecture was rejected [10,24] and has not subsequently been taken up to any significant degree by the academic community except recently as a means to an end for the support of Remote Direct Memory Access (RDMA)protocols [31].Another architectural choice which is periodically revisited is whether to perform protocol processing in user or kernel space. Druschel and Davie implemented [13] an interface which allowed user-space programs direct access to an ATM adaptor and Thekkath describes [37] an implementation of a user level TCP/IP stack over Mach. As well as performance, this work was concerned with the issues of multi-protocol co-existence and efficient operation in a micro-kernel environment. By contrast, the Jetstream/Afterburner adaptor [15] was used to implement TCP/IP in user space [15] over a monolithic kernel, as did Pratt using a firmware modified Gigabit Ethernet NIC [32]. These were essentially ports of their respective kernel protocol stacks to user level over a protected hardware interface. Hybrid models have also been proposed, see [28] for a survey and perspective. However achieving good all-round performance has proven to be elusive without a protocol stack implementation which has been expressly designed for user level operation.Over the same late-80s to mid-90s period, there was considerable parallel activity with multicomputer network interface architecture. The ATOMIC project[11] utilised components from the Mosaic multicomputer to construct a Gb/s LAN (later commercialised [3]). The multicomputer environment was somewhat less constrained than that of the ATM or distributed systems environments, application behaviour suited low-overhead user-level abstractions of communication, and these abstra...

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“…The heavy processing load is due to a combination of operating system overhead, protocol complexity, and per-octet processing on the data stream. To alleviate the end-system bottleneck one may consider new protocols [10], improved software implementation of existing protocols [5,35], parallel processing techniques [14,21,38], special protocol structures [15,30] and hardware assist [22] by offloading all or part of the protocol functions to an adaptor. This paper takes the latter approach.…”

Section: Introductionmentioning

confidence: 99%

A Reduced Operation Protocol Engine (ROPE) for a multiple-layer bypass architecture

Thia¹,

Woodside

1995

IFIP Advances in Information and Communication Technology

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-The Reduced Operation Protocol Engine (ROPE) presented here offtoads critical functions of a multiple-layer protocol stack, based on the "bypass concept" of a fast path for data transfer. The motivation for identifying this separate processing path is that it involves only a small subset of the complete protocol, which can then be implemented in hardware. Multiple-layer bypass also eliminates some inter-layer operations such as queue and buffer management, context switching and movement of data across layers, all of which are a significant overhead. ROPE is intended to support high-speed bulk data transfer. The paper describes the design of a ROPE chip for the OSI Session and Transport layer protocols, using VHDL. The design is practical in terms of chip complexity and area, using current gate array technology, and simulation shows that it can support a data rate approaching 1 gigabit per second, in a connection attached to an end-system.

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The VMP network adapter board (NAB): high-performance network communication for multiprocessors

Cited by 69 publications

References 7 publications

An operating system architecture for network processors

An operating system architecture for network processors

10Gb/s Ethernet performance and retrospective

A Reduced Operation Protocol Engine (ROPE) for a multiple-layer bypass architecture

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