The transduction method-design of logic networks based on permissible functions

Muroga, Saburo; Kambayashi, Yahiko; Lai, Hung; Culliney, Jay Niel

doi:10.1109/12.35836

Cited by 207 publications

(94 citation statements)

References 8 publications

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“…Various algorithms have been proposed to extract subsets of don't cares (see for example [68,69]). Optimization with don't cares has a close relation to other optimization methods, such as transduction [70], redundancy removal [10] and global flow analysis [71,72]. Techniques based on these methods have been successfully implemented in BooleDozer [73], a synthesis tool from IBM.…”

Section: Chapter 3 Logic Synthesismentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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KTH School of Information andCommunication Technology SE-164 40 Kista SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i elektronik fredagen den 26 januari 2007 klockan 9.00 i Sal E, Forumhuset, Kungl Tekniska högskolan, Isafjordsgatan 39, Kista. © Petra Färm, januari 2007Tryck: Universitetsservice US AB iii Abstract A conventional logic synthesis flow is composed of three separate phases: technology independent optimization, technology mapping, and technology dependent optimization. A fundamental problem with such a three-phased approach is that the global logic structure is decided during the first phase without any knowledge of the actual technology parameters considered during later phases. Although technology dependent optimization algorithms perform some limited logic restructuring, they cannot recover from fundamental mistakes made during the first phase, which often results in non-satisfiable solutions.We present a global optimization approach combining technology independent optimization steps with technology dependent objectives in an annealing-based framework. We prove that, for the presented move set and selection distribution, detailed balance is satisfied and thus the annealing process asymptotically converges to an optimal solution. Furthermore, we show that the presented approach can smoothly trade-off complex, multiple-dimensional objective functions and achieve competitive results. The combination of technology independent and technology dependent objectives is handled through dynamic weighting. Dynamic weighting reflects the sensitivity of the local graph structures with respect to the actual technology parameters such as gate sizes, delays, and power levels. The results show that, on average, the presented advanced annealing approach can improve the area and delay of circuits optimized using the Boolean optimization technique provided by SIS with 11.2% and 32.5% respectively.Furthermore, we demonstrate how the developed logic synthesis framework can be applied to two emerging technologies, chemically assembled nanotechnology and molecule cascades. New technologies are emerging because a number of physical and economic factors threaten the continued scaling of CMOS devices. Alternatives to silicon VLSI have been proposed, including techniques based on molecular electronics, quantum mechanics, and biological processes. We are hoping that our research in how to apply our developed logic synthesis framework to two of the emerging technologies might provide useful information for other designers moving in this direction.iv

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Section: Chapter 3 Logic Synthesismentioning

confidence: 99%

Integrated logic synthesis using simulated annealing

Färm

Dubrova

Kuehlmann

2011

Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI

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“…One major challenge in this context is the representation and manipulation of such don't-cares. For instance, Muroga et al [1989] proposed the concept of Compatible Sets of Permissible Functions (CSPFs), which was used by Savoj and Brayton [1990] to optimize multi-level networks composed of NOR gates. This representation was later improved by Yamashita et al [2000] and became Sets of Pairs of Functions to be Distinguished (SPFDs).…”

Section: Prior Work On Synthesis With Don't-caresmentioning

confidence: 99%

Logic synthesis and circuit customization using extensive external don't-cares

Chang

Bertacco

Markov

et al. 2010

ACM Trans. Des. Autom. Electron. Syst.

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Traditional digital circuit synthesis flows start from an HDL behavioral definition and assume that circuit functions are almost completely defined, making don't-care conditions rare. However, recent design methodologies do not always satisfy these assumptions. For instance, third-party IP blocks used in a system-on-chip are often over-designed for the requirements at hand. By focusing only on the input combinations occurring in a specific application, one could resynthesize the system to greatly reduce its area and power consumption. Therefore we extend modern digital synthesis with a novel technique, called SWEDE, that makes use of extensive external don't-cares. In addition, we utilize such don't-cares present implicitly in existing simulation-based verification environments for circuit customization. Experiments indicate that SWEDE scales to large ICs with half-million input vectors and handles practical cases well.

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“…The most common way of incorporating this type of optimization is by using the concept of "don't cares" [Brayton et al 1987;Rudell and Sangiovanni-Vincintelli 1985]. Another popular method, exploited by many researchers, is the use of "permissible functions" [Muroga et al 1989]. …”

Section: Optimization Criteriamentioning

confidence: 99%

“…Many of the current popular minimizers require an initial form of the circuit as input [Brayton et al 1987;Muroga et al 1989]. The final synthesized output can be adversely affected if a highly inefficient input circuit was provided.…”

Section: Introductionmentioning

confidence: 99%

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Behavioral synthesis of combinational logic using spectral-based heuristics

Thornton

Nair

1999

ACM Trans. Des. Autom. Electron. Syst.

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A prototype system developed to convert a behavioral representation of a Boolean function in OBDD form into an initial structural representation is described and experimental results are given. The system produces a multilevel circuit using heuristic rules based on properties of a subset of spectral coefficients. Since the behavioral description is in OBDD form, efficient methods are used to quickly compute the small subset of spectral coefficients needed for the application of the heuristics. The heuristics guide subsequent decompositions of the OBDD, resulting in an iterative construction of the structural form. At each stage of the translation, the form of the decomposition is chosen in order to achieve optimization goals.

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The transduction method-design of logic networks based on permissible functions

Cited by 207 publications

References 8 publications

Integrated logic synthesis using simulated annealing

Integrated logic synthesis using simulated annealing

Logic synthesis and circuit customization using extensive external don't-cares

Behavioral synthesis of combinational logic using spectral-based heuristics

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