The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices

Solinas, Marco; Badía, Rosa M.; Bodin, François; Cohen, Albert; Evripidou, Paraskevas; Faraboschi, Paolo; Fechner, Bernhard; Gao, Guang R.; Garbade, Arne; Girbal, Sylvain; Goodman, Daniel; Khan, Behran; Koliai, Souad; Li, Feng; Luján, Mikel; Morin, Laurent; Mendelson, Avi; Navarro, Nacho; Pop, Antoniu; Trancoso, Pedro; Ungerer, Theo; Valero, Mateo; Weis, Sebastian; Watson, Ian; Zuckermann, Stephane; Giorgi, Roberto

doi:10.1109/dsd.2013.39

Cited by 27 publications

(6 citation statements)

References 45 publications

(33 reference statements)

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“…In the context of the TERAFLUX project [19], [20], [21] such data-flow model had been extended to multiple nodes executing seamlessly thanks to the support of an appropriate memory model [22], [14]. In such memory model a combination of consumer-producer patterns [23], [24] and transactional memory [25], [26] permits a novel combination of data-flow concepts and transactions in order to address the consistency across nodes, where each node is assumed to be cachecoherent, i.e., like in a classical multi-core.…”

Section: Related Workmentioning

confidence: 99%

Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing

Giorgi

2015

2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing

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Embedded System toolchains are highly customized for a specific System-on-Chip (SoC).\ud When the application needs more performance, the designer is typically forced\ud to adopt a new SoC and possibly another toolchain.\ud The rationale for not scaling performance by using, e.g., two SoCs, is\ud that maintining most of the operations on-chip may allow for higher energy efficiency.\ud We are exploring the feasibility and trade-offs of designing and manufacturing a new Single Board Computer (SBC) that could serve flexibly for a number of current and future applications, by allowing scalability through clusters of SBCs while keeping the same programming model for the SBC.\ud This board is based on FPGAs and embedded processors, and its key points are: i) a fast custom interconnect for board-to-board communication and ii) an easily programmable environment which would allow both the off-loading of code into accelerators (either soft-IP blocks or hard-IP blocks) and, at the same time, the distribution of computation across boards.\ud A key challenge to successfully deploying this paradigm is to properly distribute the threads across several boards without the explicit intervention of the programmer.\ud In this paper we describe how to dynamically and efficiently distribute the computational threads in symbiosis with an appropriate memory model to allow the system scalability, so that we can double the performance by simply connecting two boards without i) changing the basic hardware components (e.g., to a different System-On-Chip) and ii) changing the programming model to follow the vendor specific toolchain. Our approach is to reduce data movement across boards. Our initial experiments have confirmed the feasibility of our approach

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Section: Related Workmentioning

confidence: 99%

Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing

Giorgi

2015

2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing

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“…Dataflow runtime systems have emerged as appealing solutions to create parallel programs for multi and many-core environments [6]- [11]. Dataflow paradigm is virtually supported on traditional multicore machines, where each core is a virtual Processing Element (PE) that runs the dataflow firing rule.…”

Section: A Dataflow Modelmentioning

confidence: 99%

Exploring the Equivalence between Dynamic Dataflow Model and Gamma - General Abstract Model for Multiset mAnipulation

Mello

Araújo

Alves

et al. 2019

2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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With the increase of the search for computational models where the expression of parallelism occurs naturally, some paradigms arise as options for the next generation of computers. In this context, dynamic Dataflow and Gamma -General Abstract Model for Multiset mAnipulation) -emerge as interesting computational models choices. In the dynamic Dataflow model, operations are performed as soon as their associated operators are available, without rely on a Program Counter to dictate the execution order of instructions. The Gamma paradigm is based on a parallel multiset rewriting scheme. It provides a non-deterministic execution model inspired by an abstract chemical machine metaphor, where operations are formulated as reactions that occur freely among matching elements belonging to the multiset. In this work, equivalence relations between the dynamic Dataflow and Gamma paradigms are exposed and explored, while methods to convert from Dataflow to Gamma paradigm and vice versa are provided. It is shown that vertices and edges of a dynamic Dataflow graph can correspond, respectively, to reactions and multiset elements in the Gamma paradigm. Implementation aspects of execution environments that could be mutually beneficial to both models are also discussed. This work provides the scientific community with the possibility of taking profit of both parallel programming models, contributing with a versatility component to researchers and developers. Finally, it is important to state that, to the best of our knowledge, the similarity relations between both dynamic Dataflow and Gamma models presented here have not been reported in any previous work.

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“…A major recent data-flow project that investigated how to exploit program parallelism with many-core technology is TERAFLUX [34][35][36][37][38][39]. Its challenging goal was to develop a coarse grain data-flow model to drive fine grain multithreaded or alternative/complementary computations employing Teradevice chips [40,41].…”

Section: Related Workmentioning

confidence: 99%

A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

Verdoscia

Giorgi

2016

Mathematical Problems in Engineering

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We present a new type of soft-core processor called the “Data-Flow Soft-Core” that can be implemented through FPGA technology with adequate interconnect resources. This processor provides data processing based on data-flow instructions rather than control flow instructions. As a result, during an execution on the accelerator of the Data-Flow Soft-Core, both partial data and instructions are eliminated as traffic for load and store activities. Data-flow instructions serve to describe a program and to dynamically change the context of a data-flow program graph inside the accelerator, on-the-fly. Our proposed design aims at combining the performance of a fine-grained data-flow architecture with the flexibility of reconfiguration, without requiring a partial reconfiguration or new bit-stream for reprogramming it. The potential of the data-flow implementation of a function or functional program can be exploited simply by relying on its description through the data-flow instructions that reprogram the Data-Flow Soft-Core. Moreover, the data streaming process will mirror those present in other FPGA applications. Finally, we show the advantages of this approach by presenting two test cases and providing the quantitative and numerical results of our evaluations.

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The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices

Cited by 27 publications

References 45 publications

Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing

Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing

Exploring the Equivalence between Dynamic Dataflow Model and Gamma - General Abstract Model for Multiset mAnipulation

A Data-Flow Soft-Core Processor for Accelerating Scientific Calculation on FPGAs

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