The super-diode-DRAM (SD-DRAM) — A comparative approach for CMOS memory cell to obtain low power consumption and read/write access time

Chowdhury, Paramita Saha; Pramanik, Kuheli; Sinha, Aparajita Datta; Bhattacharya, Subarna

doi:10.1109/intelcct.2017.8324022

Cited by 2 publications

(3 citation statements)

References 7 publications

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“…In addition, we have calculated the energy consumption of our proposed skyrmion-based diode. The power consumption of CMOS diodes with different designing styles is approximately 0.01-0.136 pJ [45], while for the skyrmion diodes, the power consumption is estimated to be 0.007 pJ, which is less than that of the CMOS diodes. For the analysis of power consumption of the skyrmion-based diodes, please refer to the supplementary material for details.…”

Section: Resultsmentioning

confidence: 94%

Asymmetric energy barrier induced magnetic skyrmion diodes in synthetic antiferromagnetic nanotracks

Xu,

Hu,

Zhang

et al. 2024

J. Phys. D: Appl. Phys.

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Magnetic skyrmions are nanoscale spin textures with topological protection properties, which are regarded as promising information carriers. When skyrmions move along nanotracks, their trajectories will shift if affected by skyrmion Hall effect and pinning effect. In this work, the influence of trapezoidal notches in synthetic antiferromagnetic nanotracks on the dynamics of skyrmions is investigated through micromagnetic simulation. The results exhibit that the asymmetric energy barrier induced by the asymmetric geometric structure can hinder reverse motion of skyrmions to realize the unidirectional conduction function of the diodes. Adjusting the height and inclination angle of the trapezoidal notch can effectively expand the current operating windows of the diodes, and the larger the height or inclination angle, the higher the threshold current density to overcome the pinning effect of the geometric energy barrier. Furthermore, the failure mode has a crucial impact on the implementation of skyrmion diodes. By utilizing the asymmetric structure, the forward conduction and reverse cutoff of skyrmion-based diodes can be achieved within 4 ns, with lower energy consumption than traditional diodes, resulting in high efficiency and low energy consumption of diodes. This work proposes a method for realizing the diode functionality by simply altering the geometric structure of the nanotracks, which may play an important role in the design and application of skyrmion-based diodes.

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Section: Resultsmentioning

confidence: 94%

Asymmetric energy barrier induced magnetic skyrmion diodes in synthetic antiferromagnetic nanotracks

Xu,

Hu,

Zhang

et al. 2024

J. Phys. D: Appl. Phys.

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“…The other two transistors are used for the reading stage, where one transistor permits the flow of current to perform the reading. In comparison, the second transistor positioned between the two previous transistors retains the bit to be saved through parasitic capacitances [3][4][5][6][7][8][9]. These last elements are known as the reading transistor and the storage transistor, respectively.…”

Section: Logic and Stagesmentioning

confidence: 99%

“…The extant literature shows that the 3-transistor (3T) topology consumes less power and shows lower delay values when compared to other topologies [5]; however, it is of interest to know the impact of the dimensions of the in-cell transistors on the memory performance. Therefore, this work will evaluate the electrical performance during the writing and reading stages of 8-bit eDRAM devices by varying the aspect ratio of the transistors within the cell.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of 8-bit eDRAM by varying the aspect ratio of the in-cell transistors

Rodríguez-Ibarra,

Argüelles-Lucho,

Osorio-de-la-Rosa

et al. 2024

J. Phys.: Conf. Ser.

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Embedded dynamic random-access memories (eDRAM) are widely used in the design of embedded systems for the safeguard of information during their operation. However, since these memories are installed in the same chip as the host system, it is crucial to consider their dimensioning. For this reason, in our work, the aspect ratio width and length (W/L) of complementary metal oxide semiconductor (CMOS) transistors inside 3-transistor logic cells (3T) is diversified to evaluate the effect on electrical behavior with area optimization through the figure of merit (FoM): power consumption-delay product of 8-bit memories with an operating frequency of 8.3 MHz, varying the aspect ratio of transistors inside the cell have been obtained 8.6f as lowest and 152.3f as highest FoM values. Those storage devices have been developed on 0.00085 mm2 using a 180-nm CMOS technology.

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The super-diode-DRAM (SD-DRAM) — A comparative approach for CMOS memory cell to obtain low power consumption and read/write access time

Cited by 2 publications

References 7 publications

Asymmetric energy barrier induced magnetic skyrmion diodes in synthetic antiferromagnetic nanotracks

Asymmetric energy barrier induced magnetic skyrmion diodes in synthetic antiferromagnetic nanotracks

Evaluation of 8-bit eDRAM by varying the aspect ratio of the in-cell transistors

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