The Splash 2 software environment

Arnold, Jeffrey M.

doi:10.1109/fpga.1993.279475

Cited by 50 publications

(17 citation statements)

References 9 publications

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“…Integrating Reconfigurable computing with traditional Computing systems has been a challenge since the early days of FPGAs; several machines have been designed to this direction, such as PAM [1], Splash [2], and DISC [3]. The primary drawback of all these attempts was the limited bandwidth and increased communication latency between the host general purpose processor and the reconfigurable device.…”

Section: List Of Tablesmentioning

confidence: 99%

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General Purpose Computing with Reconfigurable Acceleration

Brandon

Sourdis

Gaydadjiev

2010

2010 International Conference on Field Programmable Logic and Applications

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In this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the reconfigurable accelerator using a compiler plug-in. We define specific mechanisms for the communication between the reconfigurable device, the host general purpose processor and the main memory. The reconfigurable device is controlled by the host through system calls provided by the device driver, and initiates communication by raising interrupts; it further has direct accesses to the main memory (DMA) operating in the virtual address space. To do so, the reconfigurable device supports address translation, while the driver serves the device interrupts, ensures that shared data in the host-cache remain coherent, and handles memory protection and paging. The system is implemented using a machine which provides a HyperTransport bus connecting a Xilinx Virtex4-100 FPGA to the host. We evaluate alternative design choices of our proposal using an AES application and accelerating its most computationally intensive function. Our experimental results show that our solution is up to 5× faster than software and achieves a processing throughput equal to the theoretical maximum. n this thesis we describe a new generic approach for accelerating software functions using a reconfigurable device connected through a high-speed link to a general purpose system. In order for our solution to be generic, as opposed to related ISA extension approaches, we insert system calls into the original program to control the reconfigurable accelerator using a compiler plug-in. We define specific mechanisms for the communication between the reconfigurable device, the host general purpose processor and the main memory. The reconfigurable device is controlled by the host through system calls provided by the device driver, and initiates communication by raising interrupts; it further has direct accesses to the main memory (DMA) operating in the virtual address space. To do so, the reconfigurable device supports address translation, while the driver serves the device interrupts, ensures that shared data in the host-cache remain coherent, and handles memory protection and paging. The system is implemented using a machine which provides a HyperTransport bus connecting a Xilinx Virtex4-100 FPGA to the host. We evaluate alternative design choices of our proposal using an AES application and accelerating its most computationally intensive function. Our experimental results show that our solution is up to 5× faster than software and achieves a processing throughput equal to the theoretical maximum. Laboratory: Computer Engineering Codenumber : CE-MS

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Section: List Of Tablesmentioning

confidence: 99%

“…The host can write and read data from the FPGA(1), the FPGA can send data to the host in the form of an interrupt (2), and the FPGA can read and write data to/from the main memory(3). More precisely, the following communication types are supported:…”

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confidence: 99%

General Purpose Computing with Reconfigurable Acceleration

Brandon

Sourdis

Gaydadjiev

2010

2010 International Conference on Field Programmable Logic and Applications

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“…In past efforts, tools were provided which provided a limited form of logical to physical mapping based on signal names. An example of this is the t2 tool provided with the Splash-2 CCM [1]. This proved to be quite limiting, as signal names are merged and changed during the backend tool flow (during mapping, placement, and routing).…”

Section: Symbol Mapping Facilitymentioning

confidence: 99%

Unified Debug Environment for Adaptive Computing Systems

Hutchings¹,

Nelson²,

Wirthlin³

et al. 2003

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The public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, AFRL-IF-WP-TR-2003-1545 DISTRIBUTION/AVAILABILITY STATEMENTApproved for public release; distribution is unlimited. SUPPLEMENTARY NOTESReport contains color. ABSTRACT (Maximum 200 Words)Adaptive computing systems (ACS) are hardware systems based around FPGA technology. Historically, design and debug tools for such systems have been based on ASIC technology. However, FPGA technology provides features which suggest different approaches be used for debug. For example, readback is a feature available in many FPGA devices which provides the ability to query an executing FPGA device for its entire internal state, providing unprecedented visibility into the executing design. The central element of the debug environment developed in this work is a debug services module (DSM). It provides a unified simulation/hardware execution debug environment which allows the user to debug the executing hardware in the context of the original design environment. This means signal values in the executing hardware can be viewed and manipulated using their original signal names from the design source. In addition, the DSM provides the following support for designs running on ACS platforms: checkpointing, multitasking, remote access, and interfacing with external high-level design tools. Finally, the DSM provides support for the automatic synthesis of debug circuitry to enable rapid instrumentation of FPGA designs for debug purposes. This report summarizes the debug system and a number of the experiments completed using it. SUBJECT TERMS

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“…For instance, the Splash 2 run-time environment [5] provided both an API as well as a run-time debugging tool named t2 which could be used to execute and debug a design. The tool provided a facility to watch the values of signals as designs' clocks were stepped-a functionality utilizing the Xilinx XC4000's readback capability.…”

Section: Supplementary Notesmentioning

confidence: 99%