The SPEED cache coherence protocol for an optical multi-access interconnect architecture

Ha, Joon-Ho; Pinkston, Timothy M.

doi:10.1109/mppoi.1995.528633

Cited by 12 publications

References 20 publications

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Design of large-scale symmetric multiprocessors (SMPs) using parallel optical interconnects

Louri

Kodi

ACS/IEEE International Conference on Computer Systems and Applications, 2003. Book of Abstracts.

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In this paper, we address the primary limitation of bandwidth demands for address transaction in future cache coherent symmetric multiprocessors (SMPs). As a solution, we propose a scalable optical address sub-network called Symmetric Multiprocessor Network (SYMNET). SYMNET, not only has the ability to pipeline address requests, but also multiple address requests from different processors can propagate through the address sub-network simultaneously. This is in contrast to all electrical bus-based SMPs, where only a single request is broadcast on the physical address bus at any given point in time. The simultaneous propagation of multiple address requests in SYMNET increases the available address bandwidth and lowers the latency of the network, but the preservation of cache coherence can no longer be maintained with the usual fast snooping protocols. A modified snooping coherence protocol, Coherence in SYMNET (COSYM) is introduced to solve the coherence problem. We evaluated COSYM with a subset of Splash-2 benchmarks and compared it with the electrical bus-based MOESI protocol. Our simulation studies have shown a 5-66% improvement in execution time for COSYM as compared to MOESI for various applications. Simulations have also shown that the average latency for a transaction to complete using COSYM protocol was 5-78% better than the MOESI protocol. SYM-NET improves system performance and scalability and that additional performance gains may be attained with further improvement in optical device technology.

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Design of large-scale symmetric multiprocessors (SMPs) using parallel optical interconnects

Louri

Kodi

ACS/IEEE International Conference on Computer Systems and Applications, 2003. Book of Abstracts.

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Design of a high-speed optical interconnect for scalable shared memory multiprocessors

Kodi¹,

Louri²

Proceedings. 12th Annual IEEE Symposium on High Performance Interconnects

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This paper proposes a highly connected optical interconnect based architecture that maximizes the channel availabilifyforfuture scalable parallel computers such as Distributed Shared Memory (DSM) multiprocessors and cluster networks. As the system size increases, various messages (requests, responses and acknowledgments) increase in the network resulting in contention. This results in increasing the remote memory access latency and significantly affects the peformance of these parallel computers. As a solution, we propose an architecture called RAPID (Recon$gurable and scalable All-Photonic Interconnect for Distributed-shared memory), that provides low remote memory access latency by providing fust and eficient unicast, multicast and broadcast capabilities using a combination of aggressively designed WDM, TDM and SDM techniques. We evaluated RAPID based on network characteristics and by simulation using synthetic traffic workloads and compared it against other networks such as electrical ring, torus, mesh and hypercube networks. We found that RAPID outpeijorms all networks and satisfies most of the requirements of parallel computer design such as low latency, high bandwidth, high connectivity. and easy scalability.

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A hybrid cache coherence protocol for a decoupled multi-channel optical network: SPEED DMON

Pinkston

Proceedings of the 1996 ICPP Workshop on Challenges for Parallel Processing

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The SPEED cache coherence protocol for an optical multi-access interconnect architecture

Cited by 12 publications

References 20 publications

Design of large-scale symmetric multiprocessors (SMPs) using parallel optical interconnects

Design of large-scale symmetric multiprocessors (SMPs) using parallel optical interconnects

Design of a high-speed optical interconnect for scalable shared memory multiprocessors

A hybrid cache coherence protocol for a decoupled multi-channel optical network: SPEED DMON

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