2017
DOI: 10.1142/s2251171716410154
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The Signal Processing Firmware for the Low Frequency Aperture Array

Abstract: The signal processing firmware that has been developed for the Low Frequency Aperture Array component of the Square Kilometre Array (SKA) is described. The firmware is implemented on a dual FPGA board, that is capable of processing the streams from 16 dual polarization antennas. Data processing includes channelization of the sampled data for each antenna, correction for instrumental response and for geometric delays and formation of one or more beams by combining the aligned streams. The channelizer uses an ov… Show more

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Cited by 25 publications
(14 citation statements)
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References 8 publications
(8 reference statements)
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“…Observations were conducted using the Engineering Development Array, version 2 (EDA2: Figure 1), an array of 256 MWA antennas arranged in an SKA_low station configuration (station diameter of 35 m) and located at the MRO (Wayth et al in preparation). Analogue signal chains from the individual antennas (both polarisations; X and Y) are digitised and coarse-channelised in the firmware (Comoretto et al 2017) implemented in Tile Processing Modules (TPM; Naldi et al 2017). The coarse-channelised voltage streams are received on the data acquisition computer and signals from individual antennas are correlated using the xGPU (Clark, La Plante, & Greenhill 2011) software correlator.…”
Section: Observationsmentioning
confidence: 99%
“…Observations were conducted using the Engineering Development Array, version 2 (EDA2: Figure 1), an array of 256 MWA antennas arranged in an SKA_low station configuration (station diameter of 35 m) and located at the MRO (Wayth et al in preparation). Analogue signal chains from the individual antennas (both polarisations; X and Y) are digitised and coarse-channelised in the firmware (Comoretto et al 2017) implemented in Tile Processing Modules (TPM; Naldi et al 2017). The coarse-channelised voltage streams are received on the data acquisition computer and signals from individual antennas are correlated using the xGPU (Clark, La Plante, & Greenhill 2011) software correlator.…”
Section: Observationsmentioning
confidence: 99%
“…The firmware for the Xilinx FPGAs is described in Comoretto et al (2017). It is implemented in VHSIC Hardware Description Language (VHDL) and is based on a highly modular structure that separates the technology-dependent part of the firmware, included in an input-output (IO) module, from the actual digital signal processing (DSP) design.…”
Section: Digital Signal Pathmentioning
confidence: 99%
“…Steam-processing firmware running on the TPM boards coarsely channelises the incoming voltage streams into 512 channels of width ≈0.926 MHz; this firmware is detailed in Comoretto et al (2017). The EDA2 and AAVS2 are connected by high-speed Ethernet to a software correlator running on commercial-off-theshelf computer hardware with both stations using exactly the same rack-mounted Dell servers each with two Intel Xeon Gold 6226 2.7 GHz, 192 GB RAM, 64 TB of SSD hard-drives in RAID5 for the data, two 240 GB solid-state drives in RAID1 for the operating system, NVIDIA Tesla V100 16GB GPU, and one Mellanox ConnectX-5 dual port 40/100 Gb Ethernet card.…”
Section: Ska-low Prototype Stationsmentioning
confidence: 99%