The Scaling of Cu-Cu Hybrid Bonding For High Density 3D Chip Stacking

Kagawa, Y.; Hida, Sohta; Kobayashi, Yuka; Takahashi, Kenji; Miyanomae, S.; Kawamura, M.; Kawashima, Hiroshi; Yamagishi, H.; Hirano, Takuichi; Tatani, Keiji; Nakayama, Hiroki; Ohno, Keiichi; Iwamoto, Hayato; Kadomura, S.

doi:10.1109/edtm.2019.8731186

Cited by 24 publications

(3 citation statements)

References 4 publications

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“…The alignment error is restricted to 0.5 lm to allow proper electrical connections. In a development work, the number of Cu-Cu connections has increased to three million at 3 lm pitch [19]. As of 2020, a 1.5 lm or 0.9 lm hybrid bond pitch has been reported [52,62].…”

Section: Hybridmentioning

confidence: 99%

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Lu¹

2021

Journal of Electronic Packaging

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Numerous technology breakthroughs have been made in image sensor development in the past two decades. Image sensors have evolved into a technology platform to support many applications. Their successful implementation in mobile devices has accelerated market demand and established a business platform to propel continuous innovation and performance improvement extending to surveillance, medical, and automotive industries. This overview briefs the general camera module and the crucial technology elements of chip stacking architectures and advanced interconnect technologies. This study will also examine the role of pixel electronics in determining the chip stacking architecture and interconnect technology of choice. It is conducted by examining a few examples of CMOS Image Sensors (CIS) for different functions such as visible light detection, Single Photon Avalanche Photodiode (SPAD) for low light detection, rolling shutter and global shutter, and depth sensing and Light Detection And Ranging (LiDAR). Performance attributes of different architectures of chip stacking are overviewed. Direct bonding followed by Via-last through silicon via (Via-last TSV) and hybrid bonding (HB) technologies are identified as newer and favorable chip-to-chip interconnect technologies for image sensor chip stacking. The state-of-the-art ultra-high-density interconnect manufacturability is also highlighted.

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Section: Hybridmentioning

confidence: 99%

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Lu¹

2021

Journal of Electronic Packaging

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“…Moreover, the solder joint has destructive reliability issues with decreasing pitch, such as sidewall wetting, brittle intermetallic compound (IMC) formation, and bridge failure [1][2][3]. Thus, Cu/SiO 2 or Cu/SiCN hybrid bonds have replaced the solder joints in HPC devices [4][5][6][7][8][9][10][11][12][13][14]. However, the current temperature to achieve Cu hybrid bonding is about 300 • C. Several studies propose different approaches to achieve low-temperature bonding, including (111)-oriented nano-twinned Cu, adoption of the passivation layer, and plasma treatment [10,[15][16][17][18][19][20][21][22][23][24].…”

Section: Introductionmentioning

confidence: 99%

Measurement of Thermal Stress by X-ray Nano-Diffraction in (111)-Oriented Nanotwinned Cu Bumps for Cu/SiO2 Hybrid Joints

Hsu,

Yang,

Lin

et al. 2023

Nanomaterials

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X-ray nanodiffraction was used to measure the thermal stress of 10 µm nanotwinned Cu bumps in Cu/SiO2 hybrid structures at −55 °C, 27 °C, 100 °C, 150 °C, and 200 °C. Bonding can be achieved without externally applied compression. The X-ray beam size is about 100 nm in diameter. The Cu bump is dominated by (111) oriented nano-twins. Before the hybrid bonding, the thermal stress in Cu bumps is compressive and remains compressive after bonding. The average stress in the bonded Cu joint at 200 °C is as large as −169.1 MPa. In addition, using the strain data measured at various temperatures, one can calculate the effective thermal expansion coefficient (CTE) for the 10 µm Cu bumps confined by the SiO2 dielectrics. This study reports a useful approach on measuring the strain and stress in oriented metal bumps confined by SiO2 dielectrics. The results also provide a deeper understanding on the mechanism of hybrid bonding without externally applied compression.

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“…Current 3Dstacked structures such as high bandwidth memory (HBM) are fabricated by using a novel Cu-Cu bonding scheme [11,12]. Furthermore, they have been implemented as the interconnections in back-illuminated CMOS image sensors (BI-CIS) and image signal processors (ISPs) [13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Recrystallization and Grain Growth in Cu-Cu Joints under Electromigration at Low Temperatures

Yang,

Tran,

Chen

2023

Materials

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The behavior of recrystallization and grain growth was examined in Cu-Cu joints during electromigration at 150 °C. Recrystallization and grain growth were observed in all the joints after electromigration for 9000 h. Voiding was formed in Cu current-feeding lines and in bonding interfaces, and resistance increased with time due to the void formation. However, instead of rising abruptly, the resistance of certain Cu joints dropped after 7000 h. Microstructural analysis revealed that a large grain growth occurred in these joints at 150 °C, and the bonding interface was eliminated. Therefore, the electromigration lifetime can be prolonged for these joints.

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The Scaling of Cu-Cu Hybrid Bonding For High Density 3D Chip Stacking

Cited by 24 publications

References 4 publications

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Advancement of Chip Stacking Architectures and Interconnect Technologies for Image Sensors

Measurement of Thermal Stress by X-ray Nano-Diffraction in (111)-Oriented Nanotwinned Cu Bumps for Cu/SiO2 Hybrid Joints

Recrystallization and Grain Growth in Cu-Cu Joints under Electromigration at Low Temperatures

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