2019 Electron Devices Technology and Manufacturing Conference (EDTM) 2019
DOI: 10.1109/edtm.2019.8731186
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The Scaling of Cu-Cu Hybrid Bonding For High Density 3D Chip Stacking

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Cited by 24 publications
(3 citation statements)
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“…The alignment error is restricted to 0.5 lm to allow proper electrical connections. In a development work, the number of Cu-Cu connections has increased to three million at 3 lm pitch [19]. As of 2020, a 1.5 lm or 0.9 lm hybrid bond pitch has been reported [52,62].…”
Section: Hybridmentioning
confidence: 99%
“…The alignment error is restricted to 0.5 lm to allow proper electrical connections. In a development work, the number of Cu-Cu connections has increased to three million at 3 lm pitch [19]. As of 2020, a 1.5 lm or 0.9 lm hybrid bond pitch has been reported [52,62].…”
Section: Hybridmentioning
confidence: 99%
“…Moreover, the solder joint has destructive reliability issues with decreasing pitch, such as sidewall wetting, brittle intermetallic compound (IMC) formation, and bridge failure [1][2][3]. Thus, Cu/SiO 2 or Cu/SiCN hybrid bonds have replaced the solder joints in HPC devices [4][5][6][7][8][9][10][11][12][13][14]. However, the current temperature to achieve Cu hybrid bonding is about 300 • C. Several studies propose different approaches to achieve low-temperature bonding, including (111)-oriented nano-twinned Cu, adoption of the passivation layer, and plasma treatment [10,[15][16][17][18][19][20][21][22][23][24].…”
Section: Introductionmentioning
confidence: 99%
“…Current 3Dstacked structures such as high bandwidth memory (HBM) are fabricated by using a novel Cu-Cu bonding scheme [11,12]. Furthermore, they have been implemented as the interconnections in back-illuminated CMOS image sensors (BI-CIS) and image signal processors (ISPs) [13][14][15].…”
Section: Introductionmentioning
confidence: 99%