The SALT—Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment

Beteta, C. Abellán; Andreou, D.; Artuso, M.; Beiter, A.; Blusk, S.; Bugiel, R.; Bugiel, Szymon; Carbone, A.; Carli, I.; Chen, Bo; Conti, N.; Benedetti, F. De; Ding, S.; Ely, S.; Firlej, M.; Fiutowski, T.; Gandini, P.; Germann, D; Grieser, Nathan Allen; Idzik, M.; Jiang, Xiaojie; Krupa, W.; Li, Yiming; Li, Zhuoming; Liang, X.; Liu, Shuaiyi; Lu, Y. P.; Mackey, Lauren E.; Moroń, J.; Mountain, R.; Petruzzo, M.; Pham, H.; Schmidt, B.; Sheng, Shuqi; Norella, E. Spadaro; Świentek, K.; Szumlak, T.; Wang, Jianchun; Wilkinson, M.; Wu, Hangyi; Zhang, Feihao; Zou, Q.

doi:10.3390/s22010107

Cited by 8 publications

(5 citation statements)

References 34 publications

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“…The UT modules are composed of the silicon sensors and the front end readout electronics, glued and bonded to dataflex cables [3]. The silicon micro strip sensors have been developed in 4 different types, employed depending on their position in the layer to cope with different occupancies.…”

Section: The Upstream Trackermentioning

confidence: 99%

The operational experience of the Upstream Tracker

Tonani

2024

Proceedings of the 32nd International Workshop on Vertex Detectors — PoS(VERTEX2023)

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The LHCb experiment has faced a major upgrade in order to take data during Run 3 of the LHC with an instantaneous luminosity five times larger with respect to the previous runs. The Upstream Tracker (UT) is the new silicon strip tracking subdetector placed upstream of the LHCb magnet. It is fundamental to the particle reconstruction and plays an important role in the new software trigger. The installation of the UT has been completed in March 2023, representing a milestone for the experiment, and its commissioning phase is ongoing. This paper provides an overview of the status of the detector and details the ongoing work aimed at optimizing its functionality for the physics data acquisition.

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Section: The Upstream Trackermentioning

confidence: 99%

The operational experience of the Upstream Tracker

Tonani

2024

Proceedings of the 32nd International Workshop on Vertex Detectors — PoS(VERTEX2023)

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“…For applications in future particle physics detectors one of typical requirements regarding speed is a sampling frequency of at least 40 MHz, which corresponds to the beam crossing frequency in the world's largest accelerator, the Large Hadron Collider (LHC) at CERN [8]. Recently, the first 128-channel front-end ASIC containing a 6-bit ADC in each channel sampling at 40 MHz, has been developed for the readout of the Upstream Tracker subdetector of the LHCb experiment at CERN [9]. For various detector systems, e.g., calorimetry, a much higher amplitude resolution of 10 or even more bits is required.…”

Section: Jinst 18 P11013mentioning

confidence: 99%

An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs

Firlej,

Fiutowski,

Idzik

et al. 2023

J. Inst.

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The design and measurement results of a fast, ultra-low power, small area 10-bit SAR ADC, developed for multi-channel readout systems, in particular for applications in particle physics experiments, are discussed. A prototype ASIC was designed and fabricated in 130 nm CMOS technology and a wide spectrum of static (INL<0.4 LSB, DNL<0.3 LSB) and dynamic (ENOB=9.45) measurements was performed to study and quantify the performance of ADC. The ADC converts analogue signals with a sampling frequency up to 55 MHz and power consumption below 1 mW. The ADC works asynchronously, so no external clock is required. The ADC Figure of Merit (FOM) at 50 MHz sampling frequency is 24 fJ/conv.-step, and is the lowest among the State of the Art designs with similar technology and specifications.

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“…An ultra-low power ADC with a sampling rate of 40 MSps or more, medium-high resolution, and small pitch is required for multi-channel readout ASICs in modern and future LHC or other experiments. Recent developments of such complex readout ASICs are a 128-channel SALT ASIC for the LHCb Upstream Tracker, which contains an analogue front-end and a 6-bit 40 MSps ADC in each channel [1], or a 72-channel HGCROC ASIC for the CMS High Granularity Calorimeter, which contains an analogue front-end, a 10-bit 40 MSps ADC and a precision TDC in each channel [2]. In fact, a fast 10-bit ADC is one of the most requested and used blocks in the readout of various detector systems [2][3][4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

Firlej,

Fiutowski,

Idzik

et al. 2024

J. Inst.

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The design and measurement results of ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) prototypes in 65 nm CMOS technology are presented. Eight prototype ADCs were designed using two different switching schemes of capacitive Digital-to-Analog Converter (DAC), based on MIM or MOM capacitors, and controlled by standard or low-power SAR logic. The layout of each ADC prototype is drawn in 60 μm pitch to make it ready for multi-channel implementation. A series of measurements have been made confirming that all prototypes are fully functional, and six of them achieve very good quantitative performance. Five out of eight ADCs show both integral (INL) and differential (DNL) nonlinearity errors below 1 LSB. In dynamic measurements performed at 0.1 Nyquist input frequency, the effective number of bits (ENOB) between 8.9–9.3 was obtained for different ADC prototypes. Standard ADC versions work up to 80–90 MSps with ENOB between 8.9–9.2 bits at the highest sampling rate, while the low-power versions work up to above 50 MSps with ENOB around 9.3 bits at 40 MSps. The power consumption is linear with the sample rate and at 40 MSps it is around 400 μW for the low-power ADCs and just over 500 μW for the standard ADCs. At 80 MSps the standard ADCs consume about 1 mW.

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The SALT—Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment

Cited by 8 publications

References 34 publications

The operational experience of the Upstream Tracker

The operational experience of the Upstream Tracker

An ultra-low power 10-bit, 50 MSps SAR ADC for multi-channel readout ASICs

Ultra-low power 10-bit 50–90 MSps SAR ADCs in 65 nm CMOS for multi-channel ASICs

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