The reliability of amorphous silicon thin film transistors for LCD under DC and AC stresses

In this study, degradation of amorphous silicon thin film transistors (a-Si TFTs) under drain bias (V d ) stresses with fixed negative gate bias (V g ) has been investigated. For DC V d stress, state creation mechanism dominates the threshold voltage (V th ) degradation for relative large negative V gd (V g −V d ) while state creation and/or electron trapping dominates for positive V gd . For AC V d stress, state creation, electron trapping and hole trapping contribute to the degradation. Dominant mechanism depends on stress time, frequency and the polarity of V gd . Decreasing stress voltage suppresses state creation and/or hole trapping for −V gd condition, but enhances state creation and/or electron trapping for +V gd condition.

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The reliability of amorphous silicon thin film transistors for LCD under DC and AC stresses

Cited by 8 publications

References 13 publications

A novel low-stress driven technique for on-panel TFT gate driver

A novel low-stress driven technique for on-panel TFT gate driver

Stability of a-Si thin film transistors under negative gate bias stress

Drain bias stress-induced degradation in amorphous silicon thin film transistors with negative gate bias

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