The reconfigurable streaming vector processor (RSVP/spl trade/)

Ciricescu, Silviu; Essick, R.; Lucas, B. W.; May, P.; Moat, K.; Norris, J.; Schuette, Michael A.; Саиди, Али

doi:10.1109/micro.2003.1253190

Cited by 46 publications

(56 citation statements)

References 10 publications

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“…The application is expressed using explicit streaming constructs that identify the computational kernels and the streaming channels used to transfer data. We are using a programming model, that expresses streaming kernels using Data Flow Graphs (DFGs), and streams using stream descriptors [6]. The programmer or a high level compiler analyze the program and identify critical computational kernels in the code that will be executed by a streaming accelerator.…”

Section: Methods Overviewmentioning

confidence: 99%

An Architectural Framework for Automated Streaming Kernel Selection

Bellas

Chai

Dwyer

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

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Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedded applications. The challenge to the designer is the extensive human effort required to identify the appropriate kernels to be mapped to gates, and to implement a network of accelerators to execute the kernels. In this paper, we present a methodology to automate the selection of streaming kernels in a reconfigurable platform based on the characteristics of the application. The methodology is based on a flow graph that describes the streaming computations and communications. The flow graph is used to efficiently identify the most profitable subset of streaming kernels that optimize performance without exceeding the available area of the reconfigurable fabric.

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Section: Methods Overviewmentioning

confidence: 99%

An Architectural Framework for Automated Streaming Kernel Selection

Bellas

Chai

Dwyer

et al. 2007

2007 IEEE International Parallel and Distributed Processing Symposium

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show abstract

“…The vast majority of streaming architectures, such as Cell's SPE [Flachs et al 2005], RSVP [Ciricescu et al 2003], or Piperench [Goldstein et al 1999] are decoupled from the processing core and are highly tailored to media processing. The designs that most closely resemble HARP microarchitecturally are DySER [Govindaraju et al 2011] and ReMAP [Watkins and Albonesi 2010].…”

Section: Related Workmentioning

confidence: 99%

Energy Analysis of Hardware and Software Range Partitioning

Polychroniou

Barker

et al. 2014

ACM Trans. Comput. Syst.

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Data partitioning is a critical operation for manipulating large datasets because it subdivides tasks into pieces that are more amenable to efficient processing. It is often the limiting factor in database performance and represents a significant fraction of the overall runtime of large data queries. This article measures the performance and energy of state-of-the-art software partitioners, and describes and evaluates a hardware range partitioner that further improves efficiency.The software implementation is broken into two phases, allowing separate analysis of the partition function computation and data shuffling costs. Although range partitioning is commonly thought to be more expensive than simpler strategies such as hash partitioning, our measurements indicate that careful data movement and optimization of the partition function can allow it to approach the throughput and energy consumption of hash or radix partitioning.For further acceleration, we describe a hardware range partitioner, or HARP, a streaming framework that offers a seamless execution environment for this and other streaming accelerators, and a detailed analysis of a 32nm physical design that matches the throughput of four to eight software threads while consuming just 6.9% of the area and 4.3% of the power of a Xeon core in the same technology generation.

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“…The vast majority of streaming architectures, such as Cell's SPE [15], RSVP [10], or Piperench [16] are decoupled from the processing core and are highly tailored to media processing. The designs that most closely resemble HARP microarchitecturally are DySER [19] and ReMAP [52].…”

Section: Related Workmentioning

confidence: 99%

Navigating big data with high-throughput, energy-efficient data partitioning

Barker

Kim

et al. 2013

SIGARCH Comput. Archit. News

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The global pool of data is growing at 2.5 quintillion bytes per day, with 90% of it produced in the last two years alone [24]. There is no doubt the era of big data has arrived. This paper explores targeted deployment of hardware accelerators to improve the throughput and energy efficiency of largescale data processing. In particular, data partitioning is a critical operation for manipulating large data sets. It is often the limiting factor in database performance and represents a significant fraction of the overall runtime of large data queries.To accelerate partitioning, this paper describes a hardware accelerator for range partitioning, or HARP, and a hardware-software data streaming framework. The streaming framework offers a seamless execution environment for streaming accelerators such as HARP. Together, HARP and the streaming framework provide an order of magnitude improvement in partitioning performance and energy. A detailed analysis of a 32nm physical design shows 7.8 times the throughput of a highly optimized and optimistic software implementation, while consuming just 6.9% of the area and 4.3% of the power of a single Xeon core in the same technology generation.

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The reconfigurable streaming vector processor (RSVP/spl trade/)

Cited by 46 publications

References 10 publications

An Architectural Framework for Automated Streaming Kernel Selection

An Architectural Framework for Automated Streaming Kernel Selection

Energy Analysis of Hardware and Software Range Partitioning

Navigating big data with high-throughput, energy-efficient data partitioning

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