The Q100 Database Processing Unit

Wu, Lisa; Lottarini, Andrea; Paine, Timothy K.; Kim, Martha A.; Ross, Kenneth A.

doi:10.1109/mm.2015.51

Cited by 22 publications

(11 citation statements)

References 18 publications

(14 reference statements)

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“…There is a large body of work that bridges architecture and database methods to speed up database workloads [8-13, 18, 31, 32, 39, 41, 43, 47, 53, 56, 60, 64, 65], which includes using the use of SIMD extensions [16,37,51,52,69] and repurposing GPUs for database workloads [24,26,30,36,44,55]. There is also work on building specialized accelerators for database workloads [13,35,64,65]. From a market adoption perspective, however, most database systems today run on commodity processors.…”

Section: Related Workmentioning

confidence: 99%

Accelerating database analytic query workloads using an associative processor

Caminal

Chronis

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Database analytic query workloads are heavy consumers of datacenter cycles, and there is constant demand to improve their performance. Associative processors (AP) have re-emerged as an attractive architecture that offers very large data-level parallelism that can be used to implement a wide range of general-purpose operations. Associative processing is based primarily on efficient search and bulk update operations. Analytic query workloads benefit from data parallel execution and often feature both search and bulk update operations. In this paper, we investigate how amenable APs are to improving the performance of analytic query workloads. For this study, we use the recently proposed Content-Addressable Processing Engine (CAPE) framework. CAPE is an AP core that is highly programmable via the RISC-V ISA with standard vector extensions. By mapping key database operators to CAPE and introducing APaware changes to the query optimizer, we show that CAPE is a good match for database analytic workloads. We also propose a set of database-aware microarchitectural changes to CAPE to further improve performance. Overall, CAPE achieves a 10.8× speedup on average (up to 61.1×) on the SSB benchmark (a suite of 13 queries) compared to an iso-area aggressive out-of-order processor with AVX-512 SIMD support.

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Section: Related Workmentioning

confidence: 99%

Accelerating database analytic query workloads using an associative processor

Caminal

Chronis

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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“…The Q100 [27,28], whose NoC we consider here, is a spatial architecture for the acceleration of relational analytic queries. The Q100 is composed of a mix of processing elements (called tiles), which are specialized units that perform relational algebra operations 1 .…”

Section: Background On the Q100mentioning

confidence: 99%

“…Given the ubiquity of these workloads and the exponentially growing data sets on which they operate [16], it is crucial that their performance and efficiency be optimized. There have been multiple academic proposals to augment Database Management Systems (DBMS) with specialized hardware [27,28,4,12], as well as recent industrial designs that implement such solutions [20,18]. This paper explores how to design on-chip networks ("NoCs") for such systems.…”

Section: Introductionmentioning

confidence: 99%

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Network Synthesis for Database Processing Units

Lottarini

Edwards

Ross

et al. 2017

Proceedings of the 54th Annual Design Automation Conference 2017

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We explore on-chip network topologies for the Q100, an analytic query accelerator for relational databases. In such data-centric accelerators, interconnects play a critical role by moving large volumes of data. In this paper we show that various interconnect topologies can trade a factor of 2.5× in performance for 3.3× area. Moreover, standard topologies (e.g., ring or mesh) are not optimal. Significant prior work on network topology specialization augments generic topologies with additional dedicated links. In this paper, we present a network specialization algorithm that builds a specialized network first then introduces a generic network as a fallback. We find our algorithm produces networks that are 1.24× slower than the highest-performance generic topology considered (a fat tree), and 18% smaller than the least expensive (a double ring). Moreover, our method produces topologies that outperform those produced by others by 1.21× while being 25% smaller.

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“…H ETEROGENEOUS systems-on-chip (SoCs) include multiple processor cores and application-specific hardware components, known as hardware accelerators, to reduce power consumption and increase performance [1]- [4]. Several accelerators and accelerator-rich architectures have been developed for different applications, including neural networks [5], [6], database processing [7], [8], graph processing [9], [10], and biomedical applications [11]. There exist two main models of accelerators [12].…”

Section: Introductionmentioning

confidence: 99%

PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators

Piccolboni

Guglielmo

Carloni

2018

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Software-based attacks exploit bugs or vulnerabilities to get unauthorized access or leak confidential information. Dynamic information flow tracking (DIFT) is a security technique to track spurious information flows and provide strong security guarantees against such attacks. To secure heterogeneous systems, the spurious information flows must be tracked through all their components, including processors, accelerators (i.e., applicationspecific hardware components) and memories. We present PAGU-RUS, a flexible methodology to design a low-overhead shell circuit that adds DIFT support to accelerators. The shell uses a coarsegrain DIFT approach, thus not requiring to make modifications to the accelerator's implementation. We analyze the performance and area overhead of the DIFT shell on FPGAs and we propose a metric, called information leakage, to measure its security guarantees. We perform a design-space exploration to show that we can synthesize accelerators with different characteristics in terms of performance, cost and security guarantees. We also present a case study where we use the DIFT shell to secure an accelerator running on a embedded platform with a DIFT-enhanced RISC-V core.

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The Q100 Database Processing Unit

Cited by 22 publications

References 18 publications

Accelerating database analytic query workloads using an associative processor

Accelerating database analytic query workloads using an associative processor

Network Synthesis for Database Processing Units

PAGURUS: Low-Overhead Dynamic Information Flow Tracking on Loosely Coupled Accelerators

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