The prospects of transition metal dichalcogenides for ultimately scaled CMOS

Thiele, Sebastian; Kinberger, W.; Granzner, Ralf; Fiori, Gianluca; Schwierz, Frank

doi:10.1016/j.sse.2017.11.004

Cited by 24 publications

(22 citation statements)

References 39 publications

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“…However, the mobility suffers a severe degradation as the channel thickness scales down due to surface roughness [64][65][66]. The atomically thin nature of the 2D-TMDs, as well as the preservation of the physical properties under a short-channel condition, can address these challenges [67][68][69]. Therefore, intensive research efforts have been made to build FET based on TMDs [6,37,[70][71][72][73][74][75].…”

Section: Basic Field Effect Transistorsmentioning

confidence: 99%

Recent progress in devices and circuits based on wafer-scale transition metal dichalcogenides

Tang

Zhang

Chen

et al. 2019

Sci. China Inf. Sci.

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Section: Basic Field Effect Transistorsmentioning

confidence: 99%

Recent progress in devices and circuits based on wafer-scale transition metal dichalcogenides

Tang

Zhang

Chen

et al. 2019

Sci. China Inf. Sci.

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“…[ 15,16 ] SnS 2 has already shown performance comparable to the benchmark 2D semiconductor, MoS 2 , in applications such as FETs [ 9,12,17–19 ] and photodetectors. [ 12,20 ] Furthermore, possible reduction in short‐channel leakage [ 20,21 ] due to the larger, indirect band‐gap of SnS 2 and higher predicted mobility [ 22 ] compared to MoS 2 make SnS 2 a favorable material for electronics. Other promising applications for SnS 2 include lithium and sodium‐ion batteries, [ 23,24 ] gas sensing, [ 25 ] and various kinds of catalysis.…”

Section: Introductionmentioning

confidence: 99%

Controlling Atomic Layer Deposition of 2D Semiconductor SnS₂ by the Choice of Substrate

Mattinen

King

Brüner³

et al. 2020

Adv Materials Inter

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been explored. The 2D semiconductors, such as MoS 2 , have become the topic of particularly active research due to the crucial role of semiconductors in modern microelectronics. [7-11] Tin disulfide (SnS 2) has recently emerged as a highly interesting 2D semiconductor. [12,13] It crystallizes in the CdI 2-type 2D structure (1T phase) similar to many TMDCs [12,14] and has a fairly large, indirect band gap of approximately 2.2 eV in bulk [13,15] and 2.4−2.6 eV as a monolayer. [15,16] SnS 2 has already shown performance comparable to the benchmark 2D semiconductor, MoS 2 , in applications such as FETs [9,12,17-19] and photodetectors. [12,20] Furthermore, possible reduction in shortchannel leakage [20,21] due to the larger, indirect band-gap of SnS 2 and higher predicted mobility [22] compared to MoS 2 make SnS 2 a favorable material for electronics. Other promising applications for SnS 2 include lithium and sodium-ion batteries, [23,24] gas sensing, [25] and various kinds of catalysis. [26-28] Synthesis of 2D materials including SnS 2 is, however, a major obstacle for the realization of practical applications. An ideal synthesis method should offer high material quality, monolayer-level thickness control as well as good uniformity on large areas and complex shapes-preferably all at low processing temperatures. The substrate is an integral part of the deposition process and applications, and there are great needs both for methods capable of directly synthesizing 2D materials on different substrates, as well as for methods depositing highquality materials on single-crystalline substrates. The latter route could be combined with a transfer of the deposited material onto another substrate, if needed. [29-31] High-quality, few-layer SnS 2 has been produced from bulk crystals by micromechanical exfoliation, [12,17] but this method offers very limited control over the flake size and thickness and has extremely low throughput. Vapor-phase deposition techniques, such as chemical vapor deposition (CVD) and atomic layer deposition (ALD), are promising techniques for the deposition of 2D materials. Thus far, CVD has been mostly used to produce high-quality, isolated few-layer flakes of SnS 2 at 450-700 °C. [16,18,32,33] CVD of continuous SnS 2 films was demonstrated recently, but films below 3-4 nm in thickness remained discontinuous and even 15 nm thick films contained some holes. [34,35] ALD has been used to deposit continuous SnS 2 films with thicknesses from approximately two up to tens of monolayers. [36-41] In addition to thermal ALD processes, [36-39] Semiconducting 2D materials, such as SnS 2 , hold great promise in a variety of applications including electronics, optoelectronics, and catalysis. However, their use is hindered by the scarcity of deposition methods offering necessary levels of thickness control and large-area uniformity. Herein, a low-temperature atomic layer deposition (ALD) process is used to synthesize up to 5 × 5 cm 2 continuous, few-layer SnS 2 films on a variety of substrates, including SiO 2 /Si, S...

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“…[22] In addition, 2DLMs can provide an atomically thin channel that can effectively overcome the short-channel effects. [31,32] Therefore it provides a perfect electrolyte-gating control by taking advantage of the EDL effect and the ultrathin nature of 2DLMs. Various electrolyte materials have been used as the gate dielectrics for the 2DLMs, such as ionic liquid, [24,33,34] ion gel, [23,35,36] and polymer electrolyte.…”

Section: Introductionmentioning

confidence: 99%

“…The ultra‐high capacitance of EDL, typically 1–10 µF cm −2 , therefore results in a high density carriers accumulation in the active channel under a low operation voltage . In addition, 2DLMs can provide an atomically thin channel that can effectively overcome the short‐channel effects . Therefore it provides a perfect electrolyte‐gating control by taking advantage of the EDL effect and the ultrathin nature of 2DLMs.…”

Section: Introductionmentioning

confidence: 99%

Realizing Wafer‐Scale and Low‐Voltage Operation MoS₂ Transistors via Electrolyte Gating

Tang

Niu

Liao

et al. 2019

Adv Elect Materials

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process are highly required and under investigation. [7,8] Recently, integrated circuits based on chemical vapor deposition (CVD)-grown wafer-scale MoS 2 , a representative of TMDs, have already been realized, [9,10] which is an important step toward the practical application of lowpower and high-performance 2D electronic devices. However, the fabrication of largescale MoS 2-based circuits still remains a challenge. One of the major limits is the lack of the homogeneous high-k dielectric deposition on the TMDs without dangling bonds. [11-13] Various technical efforts have been proposed to deposit high quality Al 2 O 3 or HfO 2 dielectrics, such as seeding layer, [14] remote plasma treatment, [15] and ultraviolet-ozone exposure. [16] However, due to the existence of interfacial charge traps or dipoles during atomic layer deposition (ALD) process, a significant n-doping effect could be introduced to the TMDs channel after the top dielectric deposition. [14,17] Under this circumstance, it is difficult to realize enhancement-mode (E-mode) field-effect transistors (FETs) with a positive threshold voltage (V T), which is essential for multistage cascaded circuits. [18] Therefore, for all previously reported electrical circuits based on CVD-synthesized MoS 2 , [9,10] the gate-first technique (gate electrodes are beneath dielectric layer and transferred MoS 2 layer) is utilized to avoid the n-doping via the top dielectric deposition on MoS 2 film. Nevertheless, the gate-first technique requires an extra film transfer process in the solution, which is more challenging and rather difficult for scaling up. Nowadays, utilization of new dielectric materials for emerging semiconductors has attracted much research attention. [19-30] For example, poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) as one of the most promising ferroelectric materials, has been used in ferroelectric memories and photodetectors based on 2DLMs. [29,30] It can provide an ultrahigh electrostatic field (nearly 10 9 V m −1) in the remnant polarization. But the ferroelectric material usually requires a high gate voltage (10-20 V) to effectively drive, which greatly limits its application in low-voltage electronics. On the other hand, electrolyte material could be an alternative candidate for nanoelectronics, which can commonly serve as a dielectric layer in the FET structure. Under a positive gate voltage, for example, cations in the electrolyte accumulate at the electrolyte/semiconductor interface, and correspondingly anions gather near the Electrolyte gating, based on the electric double-layer effect, has been widely used for 2D layered materials (2DLMs), since it is capable of inducing an ultrahigh charge-carrier density while requiring only a low gate voltage. However, the wafer-scale fabrication of high-performance field effect transistors (FETs) based on electrolyte gating remains challenging, due to the lack of an appropriate electrolyte film coating technique. Wafer-scale MoS 2 FETs gated by high-quality thin electrolyte film are demonstrat...

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The prospects of transition metal dichalcogenides for ultimately scaled CMOS

Cited by 24 publications

References 39 publications

Recent progress in devices and circuits based on wafer-scale transition metal dichalcogenides

Recent progress in devices and circuits based on wafer-scale transition metal dichalcogenides

Controlling Atomic Layer Deposition of 2D Semiconductor SnS₂ by the Choice of Substrate

Realizing Wafer‐Scale and Low‐Voltage Operation MoS₂ Transistors via Electrolyte Gating

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The prospects of transition metal dichalcogenides for ultimately scaled CMOS

Cited by 24 publications

References 39 publications

Recent progress in devices and circuits based on wafer-scale transition metal dichalcogenides

Recent progress in devices and circuits based on wafer-scale transition metal dichalcogenides

Controlling Atomic Layer Deposition of 2D Semiconductor SnS2 by the Choice of Substrate

Realizing Wafer‐Scale and Low‐Voltage Operation MoS2 Transistors via Electrolyte Gating

Contact Info

Product

Resources

About

Controlling Atomic Layer Deposition of 2D Semiconductor SnS₂ by the Choice of Substrate

Realizing Wafer‐Scale and Low‐Voltage Operation MoS₂ Transistors via Electrolyte Gating