The Power of Priority: NoC Based Distributed Cache Coherency

Abstract

The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Multi Processors (CMPs). We address previously proposed CMP architectures based on Non Uniform Cache Architecture (NUCA) over NoC, analyze basic memory transactions and translate them into a set of network transactions. We first show how a simple, generic NoC which is equipped with needed module interface functionalities can provide infrastructure for the coherent access of both static and dynamic NUCA. Then we show how several low cost mechanisms incorporated into such a Vanilla NoC can facilitate CMP and boost performance of a cache coherent NUCA CMP. The basic mechanism is based on priority support embedded in the NoC, which differentiates between short control signals and long data messages to achieve a major reduction in cache access delay. The low cost Priority-based NoC is extremely useful for increasing performance of almost any other CMP transaction (i.e. uncached and cache-coherenet R/W, search in DNUCA, isolating low priority traffic, synchronization and mutual exclusion support). Priority-based NoC along with the discussed NoC interfaces are evaluated in detail using cycleaccurate CMP-NoC simulations across several SPLASH-2 benchmarks and static web content serving benchmarks showing substantial L2 cache access delay reduction and overall program speedup. For further system improvements, we introduce additional low cost NoC mechanisms that include: virtual invalidation rings, efficient store-and-forward multicast for short messages which is embedded within a wormhole NoC, and a linecache search mechanism for the efficient operation of dynamic NUCA. These mechanisms can also expedite not only cache coherency transactions but also other basic CMP transactions such as search and serialization primitives support.

Phase-Priority Based Directory Coherence for Multicore Processor

“…This is the main difference between [4] and our work. Also [4] does not show the detail implementation of this mechanism in NoC. Eisley et al [11] addressed the cache coherency problem in CMP and proposed to alter the standard directory-based system by directories implemented inside NoC router.…”

“…The majority focused on in-protocol optimizations, releasing consistency model and reducing complexity of implementation. Bolotin et al [4] propose a similar mechanism, but it just prioritizes control packets over data packets in the NoC. The main idea in [4] is to make sure that the short message can be transferred faster.…”

“…Bolotin et al [4] propose a similar mechanism, but it just prioritizes control packets over data packets in the NoC. The main idea in [4] is to make sure that the short message can be transferred faster. But the priority in PPB is used to make sure that the transaction that has been ordered can be done quickly.…”

Best of both worlds: A bus enhanced NoC (BENoC)

“…Even more sophisticated buses may include a convergecast mechanism that facilitates the efficient collection of acknowledgements or negative responses back to the initiator. Finally, the most basic service provided by the bus is a multicast (broadcast) operation: In order to deliver a message from one source to a group of (all) destinations using a basic NoC, the sender needs to generate multiple unicast messages [5]. While NoCs may include a built-in multicast mechanism (e.g., [7]), it will fall behind the simplicity and low latency of the proposed bus.…”

Efficient techniques to provide scalability for token-based cache coherence protocols.

“…In both cases, the next time the processor with the copy accesses the block, it will see the most recent value, thereby ensuring a coherent view of the memory system. Since invalidation-based coherence has been used in most recent systems (e.g., [123,99,93,35,113,18,26]), this dissertation only considers this kind of implementation.…”