The Power of Assertions in SystemVerilog

Cerny, Eduard; Dudani, Surrendra; Havlicek, John; Korchemny, Dmitry

doi:10.1007/978-1-4419-6600-1

Cited by 13 publications

(8 citation statements)

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“…It provides a powerful property language, similar to PSL [20], along with a number of other verification features. For example, random variables with arbitrary constraints may be declared, allowing concise definitions of test data generators satisfying complex invariants: There is also support for expressing test-sequence generators using a notation inspired by context-free grammars: This simple generator displays a random 10-element sequence of push and pop strings.…”

Section: Related Workmentioning

confidence: 99%

A generic synthesisable test bench

Naylor

Moore

2015

2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)

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Writing test benches is one of the most frequentlyperformed tasks in the hardware development process. The ability to reuse common test bench features is therefore key to productivity. In this paper, we present a generic test bench, parameterised by a specification of correctness, which can be used to test any design. Our test bench provides several important features, including automatic test-sequence generation and shrinking of counter-examples, and is fully synthesisable, allowing rigorous testing on FPGA as well as in simulation. The approach is easy to use, cheap to implement, and encourages the formal specification of hardware components through the reward of automatic testing and simple failure cases.

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Section: Related Workmentioning

confidence: 99%

A generic synthesisable test bench

Naylor

Moore

2015

2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE)

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“…In this section, we use the characterization to show that the original versions of the IEEE standard temporal logics PSL [Eisner andFisman 2006, 2005b] and SVA [Cerny et al 2010;IEEE 2005aIEEE , 2009] are broken in the sense that they have temporal operators that are expected to form a weak/strong pair, but that are not related semantically in the same way as W/U. We show that the source of the problem lies in the semantics of the SERE intersection and fusion operators.…”

Section: An Applicationmentioning

confidence: 99%

“…In recent years, model checking has become a mainstream tool for verification of hardware, with most industrial tools supporting one or both of the IEEE standard temporal logics PSL IEEE 2005bIEEE , 2010 and SVA [Cerny et al 2010;IEEE 2005aIEEE , 2009. In these logics, as in LTL [Pnueli 1981], temporal logic operators come in weak and strong versions.…”

Section: Introductionmentioning

confidence: 99%

Safety and Liveness, Weakness and Strength, and the Underlying Topological Relations

Eisner

Fisman

Havlicek

2014

ACM Trans. Comput. Logic

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We present a characterization that shows what it means for a formula to be a weak or strong version of another formula. We show that the weak version of a formula is not the same as Alpern and Schneider's safety component, but can be achieved by taking the closure in the Cantor topology over an augmented alphabet in which every formula is satisfiable. The resulting characterization allows us to show that the set of semantically weak formulas is exactly the set of nonpathological safety formulas. Furthermore, we use the characterization to show that the original versions of the IEEE standard temporal logics PSL and SVA are broken, and we show that the source of the problem lies in the semantics of the SERE intersection and fusion operators. Finally, we use the topological characterization to show the internal consistency of the alternative semantics adopted by the latest version of the PSL standard.

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“…If x is not exercised then (by Proposition 4) a reason is found. The position is inserted to either PrimaryList or SecondaryList according to the value of the primary flag (lines [14][15][16][17][18]. The procedure proceeds with recursive calls to the immediate predecessors with the flag primary turned off (line 20-22).…”

Section: Fig 4 Finding Primary and Secondary Reasonsmentioning

confidence: 99%

“…The IEEE standard temporal logics PSL [28,35] and SVA [18,36] use a combination of regular expressions and LTL formulas, known as suffix implication formulas (also called triggers in the definition of RELTL [17]). A suffix implication formula is of the form r ⇒ϕ where r is a regular expression and ϕ is either an LTL formula or another suffix implication formula.…”

Section: Regular Expression Based Temporal Logicmentioning

confidence: 99%

Vacuity in practice: temporal antecedent failure

Ben-David

Copty

Fisman

et al. 2015

Form Methods Syst Des

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Different definitions of vacuity in temporal logic model checking have been suggested along the years. Examining them closely, however, reveals an interesting phenomenon. On the one hand, some of the definitions require high-complexity vacuity detection algorithms. On the other hand, studies in the literature report that not all vacuities detected in practical applications are considered a problem by the system verifier. This brings vacuity detection into an undesirable situation where the user of the model checking tool may find herself waiting a long time for results that are of no interest for her. In this paper we restrict our attention to practical usage of vacuity detection. We define Temporal Antecedent Failure, an extension of antecedent failure to temporal logic, which refines the notion of vacuity. According to our experience, this type of vacuity always indicates a problem in the model, environment or property. We show how vacuity information can be derived from the automaton built for the original property, and we introduce the notion of vacuity explanation. Our experiments demonstrate that this type of vacuity as well as its reasons can be computed with a negligible increase in the overall runtime.Shoham Ben-David is grateful to the Azrieli Foundation for the award of an Azrieli Fellowship.

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The Power of Assertions in SystemVerilog

Cited by 13 publications

References 0 publications

A generic synthesisable test bench

A generic synthesisable test bench

Safety and Liveness, Weakness and Strength, and the Underlying Topological Relations

Vacuity in practice: temporal antecedent failure

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