The Potential of On-Chip Multiprocessing for QCD Machines

Bilardi, Gianfranco; Pietracaprina, Andrea; Pucci, Geppino; Schifano, Sebastiano Fabio; Tripiccione, R.

doi:10.1007/11602569_41

Cited by 30 publications

(27 citation statements)

References 27 publications

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“…In [3], authors describe a theoretical approach to analyze tradeoffs between bandwidth, memory, and processing for lattice QCD computations and provide quantitative guidelines for several architectures, including the Cell/B.E. processor.…”

Section: Prior Workmentioning

confidence: 99%

“…processor are remarkably close to the design space of the lattice QCD computations." A literature survey reveals, however, that most of the work on implementing a lattice QCD code on one of these processors is concerned with either a theoretical performance model, as in [3,2,16], or an implementation of a subset of operations extensively used in lattice QCD codes, as in [15,24,21,16]. To our knowledge, no complete lattice QCD application has been implemented on the Cell/B.E.…”

Section: Introductionmentioning

confidence: 98%

“…The Cell/B.E. in particular has attracted attention from the QCD community as it has been shown in [3] that "design parameters of the Cell/B.E. processor are remarkably close to the design space of the lattice QCD computations."…”

Section: Introductionmentioning

confidence: 99%

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The Bottom-Up Implementation of One MILC Lattice QCD Application on the Cell Blade

Shi

Kindratenko

Gottlieb

2009

Int J Parallel Prog

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We report the results of the bottom-up implementation of one MILC lattice quantum chromodynamics (QCD) application on the Cell Broadband Engine ™ processor. In our implementation, we preserve MILC's framework for scaling the application to run on a large number of compute nodes and accelerate computationally intensive kernels on the Cell's synergistic processor elements. Speedups of 3.4× for the 8 × 8 × 16 × 16 lattice and 5.7× for the 16 × 16 × 16 × 16 lattice are obtained when comparing our implementation of the MILC application executed on a 3.2 GHz Cell processor to the standard MILC code executed on a quad-core 2.33 GHz Intel Xeon processor. We provide an empirical model to predict application performance for a given lattice size. We also show that performance of the compute-intensive part of the application on the Cell processor is limited by the bandwidth between main memory and the Cell's synergistic processor elements, whereas performance of the application's parallel execution framework is limited by the bandwidth between main memory and the Cell's power processor element.

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Section: Prior Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

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The Bottom-Up Implementation of One MILC Lattice QCD Application on the Cell Blade

Shi

Kindratenko

Gottlieb

2009

Int J Parallel Prog

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“…Lattice QCD simulations is a typical and well known HPC grand challenge, where physics results are strongly limited by available computational resources [3,4]; over the years, several generations of parallel machines, optimized for LQCD, have been developed [5,6], while the development of LQCD codes running on many core architectures, in particular GPUs, has seen large efforts in the last decade [7][8][9]. Our target is to have a single code able to run on several processors without any major code change while looking for an acceptable trade-off between portability and efficiency [10].…”

Section: Introductionmentioning

confidence: 99%

Portable LQCD Monte Carlo code using OpenACC

et al. 2018

Self Cite

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Abstract. Varying from multi-core CPU processors to many-core GPUs, the present scenario of HPC architectures is extremely heterogeneous. In this context, code portability is increasingly important for easy maintainability of applications; this is relevant in scientific computing where code changes are numerous and frequent. In this talk we present the design and optimization of a state-of-the-art production level LQCD Monte Carlo application, using the OpenACC directives model. OpenACC aims to abstract parallel programming to a descriptive level, where programmers do not need to specify the mapping of the code on the target machine. We describe the OpenACC implementation and show that the same code is able to target different architectures, including state-of-the-art CPUs and GPUs.

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“…Given a computational cost C to be assigned to N nodes (so that C/N is the computational cost per node), a computational performance P per node, a local exchange of information I/N, a memory bandwith B and remote exchange of information I R and bandwith B R , in first approximation one expects that the time T for the computation at hand equals [1] …”

Section: Aim Of the Workmentioning

confidence: 99%