The positive trigger voltage lowering effect for latch-up

Lee, Jian–Hsing; Weng, Wu-Te; Shih, J.R.; Yu, K.F.; Ong, Tong-Chern

doi:10.1109/ipfa.2004.1345550

Cited by 10 publications

(1 citation statement)

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“…Several reports demonstrated that the holding voltage of SCR is mainly determined by the potential difference across the NWELL/PWELL depletion region V dep [18][19][20], which is inversely proportional to the minority carriers (electrons/holes) injected into the depletion region. While the branch path of EP-LVTSCR can extract holes/ electrons injected into the depletion region from the SCR path, thus elevating the V h of EP-LVTSCR.…”

Section: Methodsmentioning

confidence: 99%

Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS Process

et al. 2020

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Low-voltage-triggered silicon-controlled rectifier (LVTSCR) is expected to provide an electrostatic discharge (ESD) protection for a low-voltage integrated circuit. However, it is normally vulnerable to the latch-up effect due to its extremely low holding voltage. In this paper, a novel LVTSCR embedded with an extra p-type MOSFET called EP-LVTSCR has been proposed and verified in a 28-nm CMOS technology. The proposed device possesses a lower trigger voltage of ~ 6.2 V and a significantly higher holding voltage of ~ 5.5 V with only 23% degradation of the failure current under the transmission line pulse test. It is also shown that the EP-LVTSCR operates with a lower turn-on resistance of ~ 1.8 Ω as well as a reliable leakage current of ~ 1.8 nA measured at 3.63 V, making it suitable for ESD protections in 2.5 V/3.3 V CMOS processes. Moreover, the triggering mechanism and conduction characteristics of the proposed device were explored and demonstrated with TCAD simulation.

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Section: Methodsmentioning

confidence: 99%