The Photonic Bottleneck

Hinton, Kerry; Farrell, Peter M.; Tucker, Richard

doi:10.1109/ofc.2007.4348681

Cited by 7 publications

(2 citation statements)

References 15 publications

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“…We have seen that the fundamental (very loose) lower limit for the expended energy per gate is of the order of 3h + kT ln 2. An analysis similar to that in [12,45] should be performed to determine the much higher realistic lower bounds on the energy consumption for each of the proposed optical implementations, e.g., as related to the pumping of the PESI gain media.…”

Section: Discussionmentioning

confidence: 99%

“…In particular, the ideally assumed single-photon PE and detection is unrealistic in the wake of device losses, amplified spontaneous emission, and other noise sources. Most of the extra power dissipation would be related to "optical power supply" losses, i.e., the power dissipated in optically pumping the media [12,45].…”

Section: B Phase-erasure Energy Expenditurementioning

confidence: 99%

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All-optical linear reconfigurable logic with nonlinear phase erasure

et al. 2009

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We introduce a novel all-optical logic architecture whereby the gates may be readily reconfigured to reprogram their logic to implement (N)AND/(N)OR/X(N)OR. A single gate structure may be used throughout the logic circuit to implement multiple truth tables. The reconfiguration is effected by an optical reference signal. The reference may also be adapted to an arbitrary Boolean complex alphabet at the gate logic inputs and calibrated to correct gate imperfections. The all-optical gate structure is partitioned into a linear interferometric front end and a nonlinear back end. In the linear section, two optical logic inputs, along with a reference signal, linearly interfere. The nonlinear back end realizes a phase-erasure (or phase-reset) function. The reconfiguration and recalibration capabilities, along with the functional decoupling between the linear and nonlinear sections of each gate, facilitate the potential aggregation of large gate counts into logic arrays. A fundamental lower bound for the expended energy per gate is derived as 3hnu+kT ln2 Joules per bit.

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Section: Discussionmentioning

confidence: 99%

Section: B Phase-erasure Energy Expenditurementioning

confidence: 99%