The Phase-2 Upgrade of the CMS Data Acquisition

Abstract

The High Luminosity LHC (HL-LHC) will start operating in 2027 after the third Long Shutdown (LS3), and is designed to provide an ultimate instantaneous luminosity of 7:5 × 1034 cm−2 s−1, at the price of extreme pileup of up to 200 interactions per crossing. The number of overlapping interactions in HL-LHC collisions, their density, and the resulting intense radiation environment, warrant an almost complete upgrade of the CMS detector. The upgraded CMS detector will be read out by approximately fifty thousand highspeed front-end optical links at an unprecedented data rate of up to 80 Tb/s, for an average expected total event size of approximately 8 − 10 MB. Following the present established design, the CMS trigger and data acquisition system will continue to feature two trigger levels, with only one synchronous hardware-based Level-1 Trigger (L1), consisting of custom electronic boards and operating on dedicated data streams, and a second level, the High Level Trigger (HLT), using software algorithms running asynchronously on standard processors and making use of the full detector data to select events for offline storage and analysis. The upgraded CMS data acquisition system will collect data fragments for Level-1 accepted events from the detector back-end modules at a rate up to 750 kHz, aggregate fragments corresponding to individual Level- 1 accepts into events, and distribute them to the HLT processors where they will be filtered further. Events accepted by the HLT will be stored permanently at a rate of up to 7.5 kHz. This paper describes the baseline design of the DAQ and HLT systems for the Phase-2 of CMS.

The data acquisition system for the PANDA Micro-Vertex Detector

“…The ATCA carrier [5] hosts four MMB cards. The carrier board is designed using the OpenIPMC DIMM [7], which uses the JEDEC MO-244 low profile form factor employed in several ATCA cards at CERN [8][9][10]. The OpenIPMC acts as board controller [11] according to the PICMG specifications [12].…”

The CMS Barrel Calorimeter Processor demonstrator (BCPv1) board evaluation

“…The DAQ and Timing Hub (DTH) prototype, was placed in the HUB slot in an ATCA crate and was broadcasting clocks and Timing and Control Distribution Stream 2 (TCDS2) [12]. The BCPv1 successfully locked onto the TCDS2 stream, recovered the LHC clock and decoded the CMS fast commands from the data stream.…”

Clustering in the Heterogeneous Reconstruction Chain of the CMS HGCAL Detector

“…GPUs also promote the development of algorithms with better computing performance, and profit from a potentially favourable cost when compared to CPUs, per unit capacity. CMS is planning to adopt a heterogeneous High Level Trigger (HLT) farm already in Run 3 (2022Run 3 ( -2025, where ∼30% of the workflow will be offloaded to GPUs (50% and 80% by the end of Run 4 and 5, respectively) [6].…”