The ORKA-HPC Compiler—Practical OpenMP for FPGAs

Mayer, Florian; Brandner, Julian; Hellmann, Marcin; Schwarzer, Jesko; Philippsen, Michæl

doi:10.1007/978-3-030-99372-6_6

Cited by 4 publications

(1 citation statement)

References 9 publications

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“…Indeed, Fortran compilation is supported only targeting CPUs and GPUs. In [28], the authors proposed the implementation of an OpenMP-to-FPGA compiler; the main objective of the authors was to provide an easy installation process of the tool chain, support different FPGA boards and vendors, and make a modular and extensible compilation framework. This said, the authors implemented a compilation toolchain that is able to outline portions of the code that can be directly accelerated by the target FPGA.…”

Section: Related Workmentioning

confidence: 99%

Accelerating legacy applications with spatial computing devices

et al. 2022

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Heterogeneous computing is the major driving factor in designing new energy-efficient high-performance computing systems. Despite the broad adoption of GPUs and other specialized architectures, the interest in spatial architectures like field-programmable gate arrays (FPGAs) has grown. While combining high performance, low power consumption and high adaptability constitute an advantage, these devices still suffer from a weak software ecosystem, which forces application developers to use tools requiring deep knowledge of the underlying system, often leaving legacy code (e.g., Fortran applications) unsupported. By realizing this, we describe a methodology for porting Fortran (legacy) code on modern FPGA architectures, with the target of preserving performance/power ratios. Aimed as an experience report, we considered an industrial computational fluid dynamics application to demonstrate that our methodology produces synthesizable OpenCL codes targeting Intel Arria10 and Stratix10 devices. Although performance gain is not far beyond that of the original CPU code (we obtained a relative speedup of $$\times$$ × 0.59 and $$\times$$ × 0.63, respectively, for a single optimized main kernel, while only on the Stratix10 we achieved $$\times$$ × 2.56 by replicating the main optimized kernel 4 times), our results are quite encouraging to drawn the path for further investigations. This paper also reports some major criticalities in porting Fortran code on FPGA architectures.

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Section: Related Workmentioning

confidence: 99%