The optimization of H.264/AVC baseline decoder on low-cost TriMedia DSP processor

Abstract

The emerging video coding standard, H.264/AVC, exhibits the unprecedented coding performance. Comparing to traditional coders, e.g., MPEG-2 and MEPG-4 ASP, about half bitrate saving is shown in the official verification test. Such outstanding performance makes it become the video compression candidate for the upcoming HD-DVD. As a side effect, it was also blamed that H.264/AVC is much more logically complex and requires more computation power than any of the existing standards. A low-cost and efficient implementation of the international standard hence plays an important role of its success. In this paper, we realize an H.264/AVC baseline decoder by a low-cost DSP processor, i.e., Philips' TriMedia TM-1300, and illustrate that less computation demand for H.264/AVC decoding becomes feasible by using effective software core. To this end, we first consider different approaches and take advantage of SIMD instruction set to optimize critical time-consuming coding modules, such as the fractional motion compensation, spatial prediction and inverse transform. Next, we also present some other optimization approaches for entropy decoding and in-loop deblocking filtering, even though they cannot get benefits from utilizing SIMD. In our experiments, by exploiting appropriate instruction level parallelism and efficient algorithms, the decoding speed can be improved by a factor of 8~10; a CIF video sequence can be decoded at up to 19.74~28.97 fps on a 166-MHz TriMedia TM-1300 processor compared to 2.40~2.98 fps by the standard reference software.

A Multi-core Architecture Based Parallel Framework for H.264/AVC Deblocking Filters

“…We implemented both approaches on an SIMD-optimized H.264/AVC decoder. The SIMD-optimized decoder used in this study is based on our previous work [12], which achieves 45.94 frame per second (fps) decoding rate for 720p standard test sequences. The code segment of the optimized decoder is less redundant compared with that of the reference software (http://iphome.hhi.de/suehring/tml/download/ old_jm/jm73.zip) and bit-by-bit correctness of the decoded bitstreams has been verified; therefore, the experimental results are believed to be able to reflect the effectiveness of deblocking filter in practice.…”

“…Figure 1 shows the execution time distribution of a SIMD-optimized decoder/footnote. The SIMD-optimized decoder used in this study is derived on the basis of our previous work [12]. We can see that deblocking filter still accounts for 38.6% of the execution time of SIMD-optimized H.264/AVC decoding.…”

Unified UDispatch: A User Dispatching Tool for Multicore Systems

“…We adopt a parallel deblocking filter algorithm [1] and apply UUD on an H.264 decoder. Although the H.264 decoder is in nature more difficult to be parallelized, the experimental results show that the H.264 decoder [20][21] can further speed-up to 20.1%.…”

“…Therefore, we focus on improving the multithreading of deblocking filter. Based on the H.264 standard reference software [29] , the H.264 decoder has been optimized with many advanced features [20][21] . We further adopt the parallel deblocking filter algorithm [1] and apply UDispatch on it.…”

An Efficient Memory Construction Scheme for an Arbitrary Side Growing Huffman Table

“…Thus, most software approaches of entropy decoding are limited to sequential decoding because the representation of each symbol is variable in size. References [7]- [8] show that entropy decoding occupying a major portion of decoder's timing profiles. To speed up entropy decoding, however, is not as easy as to speed up the other modules of a decoding process by issuing several independent instructions simultaneously.…”