The numerical simulation of substrate and gate currents in MOS and EPROMs

Concannon, A.; Piccinini, F.; Mathewson, A.; Lombardi, C.

doi:10.1109/iedm.1995.499198

Cited by 10 publications

(6 citation statements)

References 8 publications

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“…The third factor is the magnitude of the power supply voltage; drain-to-gate potential being less than silicon bandgap is not an effective method to create enough band-bending at the semiconductor surface to allow valance band electrons to tunnel into conduction band. Gate oxide tunneling using Concannan's model [44], on the other hand, may increase transistor OFF current beyond its designed limit as it almost doubles the total OFF current as shown in Fig. 9.…”

Section: G DC Device Characteristics Of the Selected Nmos And Pmos Tmentioning

confidence: 98%

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Bindal

Naresh

Yuan

et al. 2007

IEEE Trans. Nanotechnology

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This exploratory study on vertical, undoped silicon nanowire transistors shows less power dissipation with respect to the bulk and SOI MOS transistors while yielding comparable performance. The design cycle starts with determining individual metal gate work functions for each nMOS and pMOS transistor as a function of wire radius to produce a 300 mV threshold voltage. Wire radius and effective channel length are both varied until a common body geometry is determined for both nMOS and pMOS transistors to limit OFF currents under 1 pA while producing highest ON currents. DC characteristics of the optimum and -channel transistors such as threshold voltage roll-off, DIBL and subthreshold slope are measured; simple CMOS gates including an inverter, 2-and 3-input NAND, NOR, and XOR gates, and full adder are built to measure the transient performance, power dissipation and layout area. Postlayout simulation results indicate that the worst case delay for a full adder circuit is 8.5 ps at no load and increases by 0.15 ps/aF; worst case power dissipation of the same circuit is 23.6 nW at no load and increases by 4.04 nW/aF at 1 GHz. The full adder layout area occupies approximately 0.11 m 2 .Index Terms-Low-power very large scale integration (VLSI), metal-gate transistors, nanowire transistors, vertical silicon transistors.

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Section: G DC Device Characteristics Of the Selected Nmos And Pmos Tmentioning

confidence: 98%

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Bindal

Naresh

Yuan

et al. 2007

IEEE Trans. Nanotechnology

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“…Beyond this point, the carriers are described as "hot" [12], since they are no longer in thermal equilibrium with the silicon lattice. Instead, their energy is described by an effective temperature T e , which can be modelled through a skewed Maxwell Boltzmann distribution with a high energy tail [13]. For carriers with sufficient energy, optical phonon scattering becomes the dominant energy loss mechanism and acts to saturate the velocity of the carriers, with an average speed for electrons within silicon of ≈ 10 7 cms −1 .…”

Section: Simulation Of An Emccd Register Elementmentioning

confidence: 99%

Simulations of charge transfer in Electron Multiplying Charge Coupled Devices

Bush¹,

Stefanov²,

Hall³

et al. 2014

J. Inst.

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ABSTRACT:Electron Multiplying Charge Coupled Devices (EMCCDs) are a variant of traditional CCD technology well suited to applications that demand high speed operation in low light conditions. On-chip signal amplification allows the sensor to effectively suppress the noise introduced by readout electronics, permitting sub-electron read noise at MHz pixel rates. The devices have been the subject of many detailed studies concerning their operation, however there has not been a study into the transfer and multiplication process within the EMCCD gain register. Such an investigation has the potential to explain certain observed performance characteristics, as well as inform further optimisations to their operation. In this study, the results from simulation of charge transfer within an EMCCD gain register element are discussed with a specific focus on the implications for serial charge transfer efficiency (CTE). The effects of operating voltage and readout speed are explored in context with typical operating conditions. It is shown that during transfer, a small portion of signal charge may become trapped at the semiconductor-insulator interface that could act to degrade the serial CTE in certain operating conditions.

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“…Several approximate models have been proposed in the literature for the integrand of (2.5.6) [5,6,40]; due to its simpler form, that of [40] was taken from [36] with no additional adjustment. So doing, an electron reaches the floating gate if e > ec, otherwise it is repelled back to the substate after crossing a part of the oxide region.…”

Section: Physical Modelmentioning

confidence: 99%

“…Following this concept, a number of models have been introduced in which the form of the tail is prescribed as far as its dependence on the energy is concerned, but is parametrized by functions that are available in the hydrodynamic model, typically, carrier concentration and temperature. Such models have been applied to the analysis of impact ionization [3,4] and carrier injection (e.g., [5,6]). In this way, it became possible to couple the advantage of standard methods, applicable to solving the hydrodynamic equations on realistic structures, with a finer analysis involving the use of the distribution function over specific energy ranges.…”

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confidence: 99%

Hydrodynamic simulation of semiconductor devices

Rudan

Lorenzini

Brunetti

1998

Theory of Transport Properties of Semiconductor Nanostructures

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INTRODUCTIONRecently the hydrodynamic model has become popular in the field of analysis and simulation of semiconductor devices*. The model has the merit of providing, along with the concentration and current density of the carriers, also their average energy and average energy flux. At the same time, its equations basically retain the same structure of the simpler drift-diffusion model; because of this, it has been possible to incorporate the hydrodynamic equations into existing deviceanalysis codes, thus exploiting a number of robust solution schemes already available there.The hydrodynamic model is derived by applying the moment technique to the Boltzmann transport equation (BTE) and truncating the series of moments at a suitable order. This yields a number of partial differential equations in the r, t space, specifically, the continuity equations for the carrier number, momentum, average energy and average energy flux. In this procedure, due to the integration over the wave vector space and to the series truncation, some of the information originally carried by the distribution function is lost. However, the information provided by the continuity equations indicated above is in most cases sufficient to describe the electrical behaviour of realistic semiconductor devices.It is worth noting that the term hydrodynamic model is not always given exactly the same meaning in the existing literature. What is meant here by this term is a model derived through the following steps: * Part of this work was carried out within ADEQUAT (JESSI BTl I, ESPRIT 8002) and DESSIS (ESPRIT 6075). E. Schöll (ed.), Theory of Transport Properties of Semiconductor Nanostructures

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The numerical simulation of substrate and gate currents in MOS and EPROMs

Cited by 10 publications

References 8 publications

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

The Design of Dual Work Function CMOS Transistors and Circuits Using Silicon Nanowire Technology

Simulations of charge transfer in Electron Multiplying Charge Coupled Devices

Hydrodynamic simulation of semiconductor devices

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