The New Packet Scheduling Algorithms for VOQ Switches

Baranowska, A.; Kabacinski, W.

doi:10.1007/978-3-540-27824-5_95

Cited by 8 publications

(4 citation statements)

References 9 publications

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“…Up today, several scheduling algorithms are presented in the literature [1]- [6]. It was compared and analyzed results for: iSLIP which was presented in [1], Maximal Matching with Round-Robin Selection (MMRRS) [2], [3], [4], Hierarchical Round-Robin Matching (HRRM) [5] and Parallel Iterative Matching (PIM) [6]. The efficiency is plotted in Figs.…”

Section: Simulation Results Analysismentioning

confidence: 99%

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Performance Evaluation of the MSMPS Algorithm under Different Distribution Traffic

Danilewicz,

Dziuba

2013

JTIT

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In this paper, the Maximal Size Matching with Permanent Selection (MSMPS) scheduling algorithm and its performance evaluation, under different traffic models, are described. In this article, computer simulation results under nonuniformly, diagonally and lin-diagonally distributed traffic models are presented. The simulations was performed for different switch sizes: 4×4, 8×8 and 16×16. Results for MSMPS algorithm and for other algorithms well known in the literature are discussed. All results are presented for 16×16 switch size but simulation results are representative for other switch sizes. Mean Time Delay and efficiency were compared and considered. It is shown that our algorithm achieve similar performance results like another algorithms, but it does not need any additional calculations. This information causes that MSMPS algorithm can be easily implemented in hardware.

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Section: Simulation Results Analysismentioning

confidence: 99%

“…The general VOQ switch architecture is presented in Fig. 1 [10]. In our research we use switching fabric with input queuing system (Input Queued switches), where buffers are placed at the inputs.…”

Section: Switch Architecturementioning

confidence: 99%

Performance Evaluation of the MSMPS Algorithm under Different Distribution Traffic

Danilewicz,

Dziuba

2013

JTIT

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“…One of them is iSLiP which is presented in [3]. The next one is Parallel Iterative Matching (PIM) [2], Iterative RoundRobin Matching (iRRM) [4], Maximal Matching with Random Selection (MMRS) and Maximal Matching with Round-Robin Selection (MMRRS) [5], [6], [7]. We compared all these algorithms with the new algorithm which is presented in this paper.…”

Section: Introductionmentioning

confidence: 94%

The new MSMPS Packet Scheduling Algorithm for VOQ Switches

Danilewicz

Dziuba

2012

2012 8th International Symposium on Communication Systems, Networks &Amp; Digital Signal Processing (CSNDSP)

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In this article we present the new algorithm Maximal Size Matching with Permanent Selection (MSMPS). This algorithm offers high efficiency with minimal MTD (Mean Time Delay). This algorithm based on permanent connections between inputs and outputs. When at least two connections without packets to send are found (empty connections), algorithm tries to convert them into better matching with the longest VOQ from the available. Simulations confirm that for large load our algorithm provides better efficiency than other algorithms.

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“…possible match permutations in an N × N switch, MMRS and MMRRS adopt a set of N arbitrary permutations with the property that each input can be connected to any output through this set. MMRS and MMRRS were evaluated under traffic models with Bernoulli packet arrivals with different patterns of output selection (uniform and nonuniform) [12], [13] and bursty traffic in [14] and are compared with other known algorithms like: Parallel Iterative Matching (PIM) [3], Iterative Round-Robin Matching [15], iSLIP [5], and it was shown that the MMRS and MMRRS schemes can provide higher performance than PIM and iSLIP.…”

Section: Introductionmentioning

confidence: 99%

Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches

Beldianu

Rojas‐Cessa

Oki

et al. 2009

2009 Proceedings of 18th International Conference on Computer Communications and Networks

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The performance of matching schemes for inputqueued (IQ) packet switches is mainly defined by the selection policy adopted. This policy can be aimed to produce a large weight sum for matched input-output pairs, where each inputoutput pair is assigned a weight, or to produce a large match size in the number of matched pairs, giving place to maximum weight matching or maximum size matching, respectively. However, schedulers can only provide a single match in function of the selection (of candidate ports) policy adopted and of the backlogged traffic at the input queues. A parallel match evaluator was recently proposed to provide not one but several match options at the same time. This approach evaluates several predefined and fixed matches and picks the match with the largest size. However, the fixed permutations of the evaluated matches may produce low performance under traffic with nonuniform distributions because of the limited number of choices. This paper proposes to make the parallel match evaluator configurable and two schemes to provide diverse and changeable matches such that the matches (and therefore, the evaluator) become adaptable to the traffic pattern. The proposed schemes were tested under uniform and nonuniform traffic patterns and the results show that these schemes provide high performance, even when scheduling is performed between periods of multiple time slots, or framed intervals. The proposed approach can be used for configuring slow micro-electro-mechanical (MEM) optical switch fabrics.Index Terms-packet switches, maximal weight matching, parallel matching, input-queued switch, iterative matching.

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The New Packet Scheduling Algorithms for VOQ Switches

Cited by 8 publications

References 9 publications

Performance Evaluation of the MSMPS Algorithm under Different Distribution Traffic

Performance Evaluation of the MSMPS Algorithm under Different Distribution Traffic

The new MSMPS Packet Scheduling Algorithm for VOQ Switches

Re-Configurable Parallel Match Evaluators Applied to Scheduling Schemes for Input-Queued Packet Switches

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