The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer

Palumbo, Francesca; Carta, Nicola; Raffo, Luigi

doi:10.1109/dasip.2011.6136876

Cited by 15 publications

(9 citation statements)

References 8 publications

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“…Therefore, automatic methodologies are of paramount importance. It has been already demonstrated in [25] and in [26] that combining the dataflow formalism with the coarse-grained design paradigm may be extremely beneficial to generate efficient and flexible datapaths, which can be integrated within co-processing units. The tool used within those studies, the Multi-Dataflow Composer (MDC) tool, is a software framework for the automatic generation of reconfigurable platforms.…”

Section: B Co-processing Units: Automatic Generationmentioning

confidence: 98%

Automatic generation of dataflow-based reconfigurable co-processing units

Palumbo

2014

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing

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Hardware accelerators are widely adopted to speed up computationally onerous applications. However their design is not trivial, especially if multiple applications/kernels need to be served. To this aim the Multi-Dataflow Composer (MDC) tool can be adopted to generate the internal computing core of flexible and reconfigurable hardware accelerators. Nevertheless, MDC is not able, as it is, to deploy ready to use accelerators. To address this lack, we conceived a fully automated design flow for coarse-grained reconfigurable and memory-mapped hardware accelerators, which required: a) the definition of a generic co-processing template, the Template Interface Layer; b) the extension of the MDC tool to characterize such a template and deploy the accelerators. This methodology represents, within MPEG Reconfigurable Video Coding studies, the first framework for the automatic generation of reconfigurable hardware accelerators and, as it will be discussed, it may be beneficial also in other contexts of execution with fairly limited adjustments. Results validated the proposed approach in a real use case scenario, comparing the automatically generated co-processor with a previous custom one.

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Section: B Co-processing Units: Automatic Generationmentioning

confidence: 98%

Automatic generation of dataflow-based reconfigurable co-processing units

Palumbo

2014

Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing

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“…It was meant to address the difficulty of mapping different applications onto a coarse-grained reconfigurable architecture [3,6]. Its final goal [10,11] is to automate such a mapping process while minimizing hardware resources, with consequent area/energy saving. To assemble the coarse-grained reconfigurable multi-functional system, MDC exploits the modularity offered by the dataflow models processing a set of input DPNs (representing the different functionalities to be implemented).…”

Section: The Multi-dataflow Composer Toolchainmentioning

confidence: 99%

Automated power gating methodology for dataflow-based reconfigurable systems

Fanni

Raffo

et al. 2015

Proceedings of the 12th ACM International Conference on Computing Frontiers

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Modern embedded systems designers are required to implement efficient multi-functional applications, over portable platforms under strong energy and resources constraints. Automatic tools may help them in challenging such a complex scenario: to develop complex reconfigurable systems while reducing time-to-market. At the same time, automated methodologies can aid them to manage power consumption. Dataflow models of computation, thanks to their modularity, turned out to be extremely useful to these purposes. In this paper, we will demonstrate as they can be used to automatically achieve power management since the earliest stage of the design flow. In particular, we are focussing on the automation of power gating. The methodology has been evaluated on an image processing use case targeting an ASIC 90 nm CMOS technology

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“…The Multi-Dataflow Composer (MDC) tool [21,22], which assembles the heterogeneous CGR substrate, acquires the dataflow descriptions of the kernels and applies datapath merging techniques to achieve resources minimization. An example of CGR system assembled with the MDC approach is shown Fig.…”

Section: System Composition and Mappingmentioning

confidence: 99%

Power and clock gating modelling in coarse grained reconfigurable systems

Fanni

Meloni

et al. 2016

Proceedings of the ACM International Conference on Computing Frontiers

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Power reduction is one of the biggest challenges in modern systems and tends to become a severe issue dealing with complex scenarios. To provide high-performance and exi-bility, designers often opt for coarse-grained reconfigurable (CGR) systems. Nevertheless, these systems require specific attention to the power problem, since large set of resources may be underutilized while computing a certain task. This paper focuses on this issue. Targeting CGR devices, we propose a way to model in advance power and clock gat-ing costs on the basis of the functional, technological and architectural parameters of the baseline CGR system. The proposed ow guides designers towards optimal implemen-Tations, saving designer effort and time

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The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer

Cited by 15 publications

References 8 publications

Automatic generation of dataflow-based reconfigurable co-processing units

Automatic generation of dataflow-based reconfigurable co-processing units

Automated power gating methodology for dataflow-based reconfigurable systems

Power and clock gating modelling in coarse grained reconfigurable systems

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