The Monarch parallel processor hardware design

Rettberg, R. D.; Crowther, W. R.; Carvey, P.P.; Tomlinson, Raymond S.

doi:10.1109/2.55467

Cited by 64 publications

(12 citation statements)

References 5 publications

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“…Only a few parallel architectures feature networks which may discard packets; among these exceptional cases are the BBN Butterfly [25], the BBN Monarch [26], and the Metro router architecture [4]. Each of these implements a circuit-switched network which discards packets in response to collisions or network faults.…”

Section: Related Workmentioning

confidence: 99%

A lightweight idempotent messaging protocol for faulty networks

Brown

Grossman

Knight

2002

Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures

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As parallel machines scale to one million nodes and beyond, it becomes increasingly difficult to build a reliable network that is able to guarantee packet delivery. Eventually large systems will need to employ fault-tolerant messaging protocols that afford correct execution in the presence of a lossy network. In this paper we present a lightweight protocol that preserves message idempotence and is easy to implement in hardware. We identify the requirements for a correct implementation of the protocol. Experiments are performed in simulation to determine implementation parameters that optimize performance. We find that an aggressive implementation on a fat tree network results in a slowdown of less than 2x compared to buffered wormhole routing on a fault-free network.

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Section: Related Workmentioning

confidence: 99%

A lightweight idempotent messaging protocol for faulty networks

Brown

Grossman

Knight

2002

Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures

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“…The difficulty encountered in scaling the shared-memory MIMD approach to large PE counts [31] and the large number of potential architectural solutions to problems encountered in achieving scalable distributed memory MIMD performance led us in the distributed memory direction for the Mayfly effort. There are a number of other research and commercial machines that have also chosen the message-passing distributed-memory MIMD approach [34,9,29,18,27].…”

Section: Davismentioning

confidence: 99%

Mayfly: A general-purpose, scalable, parallel processing architecture

Davis

1992

Lisp and Symbolic Computation

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Abstract. The Mayfly is a scalable general-purpose parallel processing system being designed at HP Laboratories, in collaboration with colleagues at the University of Utah. The system is intended to efficiently support parallel variants of modern programming languages such as Lisp, Prolog, and Object Oriented Programming models. These languages impose a common requirement on the hardware platform to support dynamic system needs such as runtime type checking and dynamic storage management. The main programming language for the Mayfly is a concurrent dialect of Scheme. The system is based on a distributed-memory model, and communication between processing elements is supported by message passing. The initial prototype of Mayfly will consist of 19 identical processing elements interconnected in a hexagonal mesh structure. In order to achieve the goal of scalable performance, each processing element is a parallel processor as well, which permits the application code, runtime operating system, and communication to all run in parallel. A 7 processing element subset of the prototype is presently operational. This paper describes the hardware architecture after a brief background synopsis of the software system structure. I n t r o d u c t i o nThe goal of the M a y f l y effort was to produce a general-purpose scalable parallel processor. More specifically we sought to produce a machine that: Would achieve increased performance, primarily through parallelism, for both numeric and symbolic computations.Would exhibit a reasonable performance improvement as the number of processing elements in the system was increased. The argument of what constitutes reasonable performance scaling is difficult to precisely quantify and subsequently this issue will be addressed in more detail, but it is clear that logarithmic performance scaling is not generally cost-effective, and that achieving linear speedup over a wide range of applications would be ideal but perhaps impossible to attain.

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“…In a d-dilated butter y, each channel consists of d wires. Because it is harder to congest a channel than it is to congest a single wire in a butter y, dilated butter ies are better routing networks than simple butter ies 14,16,27]. 1 Throughout this paper, log N denotes log 2 N.…”

Section: Dilated Butter Iesmentioning

confidence: 99%

Fast algorithms for routing around faults in multibutterflies and randomly-wired splitter networks

Leighton

Maggs

1992

IEEE Trans. Comput.

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{This paper describes simple deterministic O(log N)-step algorithms for routing permutations of packets in multibutter ies and randomlywired splitter networks. The algorithms are robust against faults (even in the worst case), and are e cient from a practical point of view. As a consequence, we nd that the multibutter y is an excellent candidate for a high-bandwidth low-diameter switching network underlying a sharedmemory machine.

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The Monarch parallel processor hardware design

Cited by 64 publications

References 5 publications

A lightweight idempotent messaging protocol for faulty networks

A lightweight idempotent messaging protocol for faulty networks

Mayfly: A general-purpose, scalable, parallel processing architecture

Fast algorithms for routing around faults in multibutterflies and randomly-wired splitter networks

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