The modular pipeline fast Fourier transform algorithm and architecture

El-Khashab, A.M.; Swartzlander, Earl E.

doi:10.1109/acssc.2003.1292228

Cited by 8 publications

(7 citation statements)

References 8 publications

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“…El-Khasahab, et al developed the modular pipeline FFT detailed in [18]- [20]. The N-point modular pipeline FFT consists of two N -point FFT modules joined by a specialized center element.…”

Section: The Modular Pipelinementioning

confidence: 99%

“…Further, the MDC pipeline FFT utilizes (r+1)N/2 -r delay elements, and (r-1) (log r N -1) real multipliers and roughly 2(r-1) (log r N -1) adders. Table 14 summarizes the hardware and timing complexities for FFT pipeline architectures discussed in references [18], [20]. The table also illustrates the complexities for the switch based architecture (shown in the last row of the table.)…”

Section: Comparison With Other Fft Pipelinesmentioning

confidence: 99%

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The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm

Mohd¹,

Swartzlander

Aziz³

2009

VLSI-SoC: Advanced Topics on Systems on a Chip

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Abstract. This chapter examines the superscalar pipeline Fast Fourier Transform algorithm and architecture. The algorithm presents a memory management scheme that avoids memory contention throughout the pipeline stages. The fundamental algorithm, a switch-based FFT pipeline architecture and an example 64-point FFT implementation are presented. The pipeline consists of log 2 N stages, where N is number of FFT points. Each stage can have M Processing Elements (PEs.) As a result, the architecture speed up is M*log 2 N. The pipeline algorithm is configurable to any M > 1.

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“…El-Khasahab, et al developed the modular pipeline FFT detailed in [18]- [20]. The N-point modular pipeline FFT consists of two N -point FFT modules joined by a specialized center element.…”

Section: The Modular Pipelinementioning

confidence: 99%

Section: Comparison With Other Fft Pipelinesmentioning

confidence: 99%

The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm

Mohd¹,

Swartzlander

Aziz³

2009

VLSI-SoC: Advanced Topics on Systems on a Chip

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“…The SASP implements a pipeline FFT algorithm [6]. A radix-4 FFT using log 4 (N ) stages was chosen in order to improve the speed efficiency [7], [8]. All stages of a radix-4 FFT use a basic module with 4 weighted inputs (twiddle factors) and 4 outputs.…”

Section: The Sampled Analog Signal Processormentioning

confidence: 99%

“…A pipeline implementation consists in using one basic module per stage which runs with two processing phases [7], [8]:…”

Section: The Sampled Analog Signal Processormentioning

confidence: 99%

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65nm CMOS Circuit design of a sampled analog signal processor dedicated to RF applications

Rivet

Deval

Bégueret

et al. 2008

2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference

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Abstract-The Software-Defined Radio (SDR) concept aims at designing a re-configurable radio architecture accepting all cellular or non-cellular standards working in the 0-5 GHz frequency range. Some technical challenges have to be solved in order to address this concept. A fully digital SDR system implying an A/D conversion close to the antenna is not feasible in the case of mobile terminal. This paper presents the design of an Analog Processor which process RF signal in order to select and convert into digital only the desired RF signal envelope. It uses the principle of a Fast Fourier Transform (FFT) to carry out basic analog functions with high accuracy at a low power consumption. Schematic and Post Layout Simulations are exhibited. Estimated die area and power consumption are numbered.Index Terms-analog signal processing, software-defined radio, cognitive radio, sampled analog signal processor.

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An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor

Wang¹,

Li²

2007

J Sign Process Syst Sign Image

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Fast Fourier Transform (FFT) and its inverse transform (IFFT) are commonly used tools for digital signal processing. They are widely used in various communication systems, especially the communication system based on orthogonal frequency division multiplexing (OFDM) technology. Reducing the cost of multiplier area can effectively spare the area of FFT because multipliers take up the mainly cost of the hardware. To solve the above problems, inexact multiplier for FFT, with lower area cost and low SQNR loss compared to a conventional exact FFT processor, is proposed. Comparison results show that the proposed FFT processor has good property for applications like DVB-T, LTE.

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The modular pipeline fast Fourier transform algorithm and architecture

Cited by 8 publications

References 8 publications

The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm

The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm

65nm CMOS Circuit design of a sampled analog signal processor dedicated to RF applications

An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor

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