The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor

Agarwal, Anant; Chaiken, David; Johnson, Kirk L.; Kranz, David; Kubiatowicz, John; Kurihara, Kenichi; Lim, Beng-Hong; Maa, Gino K.; Nussbaum, Daniel A.; Parkin, Michael; Yeung, Donald

doi:10.1007/978-1-4615-3604-8_13

Cited by 118 publications

(49 citation statements)

References 25 publications

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“…In practice, since the secondary cache is under tight control of the main microprocessor and needs to remain small and fast for uniprocessor nodes, most SCI-based architectures implement this data structure as a duplicate set of cache tags in the main memory system of the multiprocessor. 1 The distributed nature of the SCI protocol has two main advantages. First, it reduces the size of the directory on each node.…”

Section: Base Cc-numa: Scimentioning

confidence: 99%

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Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors

SoundararajanVijayaraghavan

HeinrichMark

VergheseBen³

et al. 1998

SIGARCH Comput. Archit. News

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Given the limitations of bus-based multiprocessors, CC-NUMA is the scalable architecture of choice for shared-memory machines. The most important characteristic of the CC-NUMA architecture is that the latency to access data on a remote node is considerably larger than the latency to access local memory. On such machines, good data locality can reduce memory stall time and is therefore a critical factor in application performance.In this paper we study the various options available to system designers to transparently decrease the fraction of data misses serviced remotely. This work is done in the context of the Stanford FLASH multiprocessor. FLASH is unique in that each node has a single pool of DRAM that can be used in a variety of ways by the programmable memory controller. We use the programmability of FLASH to explore different options for cache-coherence and datalocality in compute-server workloads. First, we consider two protocols for providing base cache-coherence, one with centralized directory information (dynamic pointer allocation) and another with distributed directory information (SCI). While several commercial systems are based on SCI, we find that a centralized scheme has superior performance. Next, we consider different hardware and software techniques that use some or all of the local memory in a node to improve data locality. Finally, we propose a hybrid scheme that combines hardware and software techniques. These schemes work on the same base platform with both user and kernel references from the workloads. The paper thus offers a realistic and fair comparison of replication/migration techniques that has not previously been feasible. IntroductionShared-memory multiprocessors are increasingly used as compute servers. These systems enable efficient usage of computing resources through the aggregation and tight coupling of CPU, memory and I/O. As processors get faster, the shared bus becomes a bandwidth bottleneck in bus-based multiprocessors. CC-NUMA (Cache-Coherent with Non-Uniform Memory Access time) machines remove this architectural limitation and provide a scalable shared-memory architecture. A typical design has a number of nodes, each node consisting of one or more processors and a portion of the machine's global main memory. The nodes are connected using scalable interconnect technology, and cachecoherence is maintained using a directory-based scheme. The most important attribute of the CC-NUMA architecture is that the latency to access data on a remote node is considerably larger than the latency to access local memory. The ratio of remote to local access times can be as small as 2 (or 3) to 1 for the SGI Origin or as high as 8 to 1 for the Sequent STiNG. On such machines, good data locality can reduce memory stall time and is therefore a critical factor in application performance. However, the dynamic nature of compute-server workloads makes it difficult to ensure good data locality. For example, static data-placement schemes do not work because the operating system moves proce...

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Section: Base Cc-numa: Scimentioning

confidence: 99%

“…Examples include commercial machines such as Sequent STiNG [18], HP Exemplar [4], Data General NUMALiiNE [6], and SGI Origin 2000 [16], and academic prototypes such as Alewife [1], DASH [17], and FLASH [15].…”

Section: Introductionmentioning

confidence: 99%

Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors

SoundararajanVijayaraghavan

HeinrichMark

VergheseBen³

et al. 1998

SIGARCH Comput. Archit. News

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“…A processor node consists of three major elements: a processing element, a local memory, and a network interface. An interconnection network is a graph in which the vertices are the processor nodes and the edges are the communication links 2 . Figure 1 shows the main features of the network interface for a generic processor node.…”

Section: Preliminariesmentioning

confidence: 99%

ROMM routing on mesh and torus networks

Nesson

Johnsson

1995

Proceedings of the Seventh Annual ACM Symposium on Parallel Algorithms and Architectures - SPAA '95

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ROMM is a class of Randomized, Oblivious, Multi{phase, Minimal routing algorithms. ROMM routing o ers a potential for improved performance compared to both fully randomized algorithms and deterministic oblivious algorithms, under both light and heavy loads. ROMM routing also offers close to best case performance for many common routing problems. In previous work, these claims were supported by extensive simulations on binary cube networks 30, 31]. Here we present analytical and empirical results for ROMM routing on wormhole routed mesh and torus networks. Our simulations show that ROMM algorithms can perform several representative routing tasks 1.5 to 3 times faster than fully randomized algorithms, for medium{sized networks. Furthermore, ROMM algorithms are always competitive with deterministic, oblivious routing, and in some cases, up to 2 times faster.1 Introduction E cient data motion has been critical in high performance computing as long as computers have been in existence. Massively parallel computers use a sparse interconnection network between processing nodes with local memories. Minimizing the potential for high congestion of communication links is an important goal in the design of routing algorithms and networks. Moreover, the packaging technology introduces constraints on the data motion bandwidth at module boundaries, such as chips and boards.These constraints suggest that preserving locality of reference with careful data allocation and minimizing network load by using minimal algorithms are desirable objectives. However, it is important to note that minimal algorithms and locality preserving data mappings do not always guarantee the best routing times. In fact, for certain problems, non{minimal routing algorithms and data allocations which do not preserve locality can utilize more of the available network bandwidth and cause less communication link congestion, without the corresponding increase in demand for network bandwidth.In this paper, we report on a class of minimal algorithms designed to keep the risk of severe congestion low

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“…Write-bu ering which can merge data from the processor with returning data from memory 3 Context-dependent fetch-bu ers in which to place the results of global instruction fetches.…”

Section: Signaling With Block Multithreadingmentioning

confidence: 99%

Closing the window of vulnerability in multiphase memory transactions

Kubiatowicz¹,

Chaiken²,

Agarwal³

1992

SIGPLAN Not.

Self Cite

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Multiprocessor architects have begun to explore several mechanisms such as prefetching, context-switching and software-assisted dynamic cache-coherence, which transform single-phase memory transactions in conventional memory systems into multiphase operations. Multiphase operations introduce a window of vulnerability in which data can be invalidated before it is used. Losing data due to invalidations introduces damaging livelock situations. This thesis discusses the origins of the window of vulnerability and proposes an architectural framework that closes it. The framework employs fully-associative transaction-bu ers and an algorithm called thrashlock. It has been implemented as one facet of the Alewife machine, a large-scale cache-coherent multiprocessor.

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The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor

Cited by 118 publications

References 25 publications

Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors

Flexible use of memory for replication/migration in cache-coherent DSM multiprocessors

ROMM routing on mesh and torus networks

Closing the window of vulnerability in multiphase memory transactions

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