The ManArray/sup TM/ embedded processor architecture

Pechanek, G.G.; Vassiliadis, S.

doi:10.1109/eurmic.2000.874652

Cited by 24 publications

(21 citation statements)

References 8 publications

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“…The algorithm initially performs partial scheduling of all frequency configurations for "STEP" instructions (Alg.1 lines 11,[14][15][16][17][18][19][20]. This determines the best configuration and stores it into "BFC".…”

Section: The Drivermentioning

confidence: 99%

“…This determines the best configuration and stores it into "BFC". For the rest of the algorithm, each frequency configuration in the neighboring set of "BFC" (lines 13,14) gets partially scheduled for "STEP" instructions and evaluated (lines 15,16). The best performing of the neighbors gets stored into "BFC" (line 19).…”

Section: The Drivermentioning

confidence: 99%

“…Clustered VLIW processors operate at an attractive power/performance ratio point. Examples are the Texas Instrument's VelociTI, HP/ST's Lx [6], Analog's TigerSHARC [7], and BOPS' ManArray [15].…”

Section: Introductionmentioning

confidence: 99%

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UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores

Porpodas

Cintra

2013

Languages and Compilers for Parallel Computing

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Abstract. Clustered VLIW processors are scalable wide-issue statically scheduled processors. Their design is based on physically partitioning the otherwise shared hardware resources, a design which leads to both high performance and low energy consumption. In traditional clustered VLIW processors, all clusters operate at the same frequency. Heterogeneous clustered VLIW processors however, support dynamic voltage and frequency scaling (DVFS) independently per cluster. Effectively controlling DVFS, to selectively decrease the frequency of clusters with a lot of slack in their schedule, can lead to significant energy savings. In this paper we propose UCIFF, a new scheduling algorithm for heterogeneous clustered VLIW processors with software DVFS control, that performs cluster assignment, instruction scheduling and fast frequency selection simultaneously, all in a single compiler pass. The proposed algorithm solves the phase ordering problem between frequency selection and scheduling, present in existing algorithms. We compared the quality of the generated code, using both performance and energy-related metrics, against that of the current state-of-the-art and an optimal scheduler. The results show that UCIFF produces better code than the state-ofthe-art, very close to the optimal across the mediabench2 benchmarks, while keeping the algorithmic complexity low.

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Section: The Drivermentioning

confidence: 99%

Section: The Drivermentioning

confidence: 99%

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UCIFF: Unified Cluster Assignment Instruction Scheduling and Fast Frequency Selection for Heterogeneous Clustered VLIW Cores

Porpodas

Cintra

2013

Languages and Compilers for Parallel Computing

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“…The use of clustering has been popular especially in the DSP market, including Texas Instruments' TMS320C6x [36], Analog Devices' TigerSHARC [19], BOPS's Man Array [31], HP/ST's Lx [17], and Equator's MAP1000 [20]. All of these processors use a statically scheduled, clustered microarchitecture.…”

Section: Introductionmentioning

confidence: 99%

AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures

Aletà

Codina²,

Sánchez

et al. 2009

IEEE Trans. Comput.

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Abstract-This paper presents AGAMOS, a technique to modulo schedule loops on clustered microarchitectures. The proposed scheme uses a multilevel graph partitioning strategy to distribute the workload among clusters and reduces the number of intercluster communications at the same time. Partitioning is guided by approximate schedules (i.e., pseudoschedules), which take into account all of the constraints that influence the final schedule. To further reduce the number of intercluster communications, heuristics for instruction replication are included. The proposed scheme is evaluated using the SPECfp95 programs. The described scheme outperforms a state-of-the-art scheduler for all programs and different cluster configurations. For some configurations, the speedup obtained when using this new scheme is greater than 40 percent, and for selected programs, performance can be more than doubled.

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“…The use of clustering is especially noticeable in the DSP market, including Texas Instruments' TMS320C6x [23], Analog Devices'TigerSHARC [10], BOPS's Man Array [19], HP/ST's Lx [9] and Equator's MAP1000 [11]. All of these processors use a statically-scheduled, clustered, microarchitecture.…”

Section: Introductionmentioning

confidence: 99%