The m-pancycle-connectivity of a WK-Recursive network

Fang, Jywe-Fei; Wang, Yuh-Rau; Huang, Hui-Ling

doi:10.1016/j.ins.2007.04.013

Cited by 18 publications

(11 citation statements)

References 24 publications

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“…Several topologies, such as 2D mesh and Torus have been proposed in the field of parallel computing and adopted in NoC research [18]. Recently, an attractive topology called WK-recursive network has received considerable attention in parallel community due to its many favorable properties, such as high degree of regularity, symmetry and efficient communication, scalability, and ease of extendibility [6]. This topology has initially been proposed for VLSI implementation [22] and later adapted as a network topology for parallel computers [5,15,23].…”

Section: Wk-recursive Network: An Overviewmentioning

confidence: 99%

“…More precisely, a WK-recursive network with amplitude W and level L, denoted by a WK(W, L), can be recursively constructed [6]. A WK(W, 0) is a vertex with W free edges.…”

Section: Wk-recursive Network: An Overviewmentioning

confidence: 99%

“…WK-recursive network was initially proposed in [22] as a network for VLSI implementation. Since the topology has many attractive properties, such as high degree of regularity, symmetry and efficient communication, WK-Recursive networks have received considerable attention in parallel computing community (see [5,6,15]). In addition to these interesting properties that suit NoC, for any specified degree, it can be expanded to an arbitrary level without reconfiguring the edges.…”

Section: Introductionmentioning

confidence: 99%

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An interconnection architecture for network-on-chip systems

et al. 2008

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Network on Chip (NoC) is a discipline research path that primarily addresses the global communication in System on Chip (SoC). It is inspired and uses the same routing and switching techniques needed in multi-computer networks. Current shared-bus based on-chip communication architectures generally have limited scalability due to the nature of the buses especially when complex on-chip communication SoC is needed. The main goal is to have a dedicated communication infrastructure in the system that can scale up while minimizing the area and power. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we introduce a new NoC architecture by adapting a recursive topology structure. An experimental study is performed to compare this structure with basic NoC topologies represented by 2D mesh and Spidergon. The analysis illustrates the main features of this topology and its unique benefits. The simulation results show that recursive network outperforms 2D mesh and Spidergon in main performance metrics.

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Section: Wk-recursive Network: An Overviewmentioning

confidence: 99%

“…More precisely, a WK-recursive network with amplitude W and level L, denoted by a WK(W, L), can be recursively constructed [6]. A WK(W, 0) is a vertex with W free edges.…”

Section: Wk-recursive Network: An Overviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An interconnection architecture for network-on-chip systems

et al. 2008

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“…That is why many parallel algorithms have been devised based on them [13,14,16]. Many researchers have discussed how to embed cycles and paths into various interconnection networks [1,3,6,7,9,17,22,23]. A graph is Hamiltonian if it embeds a Hamiltonian cycle that contains each vertex exactly once [4].…”

mentioning

confidence: 99%

“…A new cycle embedding aspect called pancycle-connectivity that combines the concepts of vertex-pancyclicity and panconnectivity has been proposed by Fang et al [7]. A graph G is pancycle-connected if every two distinct vertices x and y of G are contained by a cycle of every length ranging from the length of the smallest cycle that contains x and y to N .…”

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confidence: 99%

The panconnectivity and the pancycle-connectivity of the generalized base-b hypercube

Huang

Fang

2008

J Supercomput

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The interconnection network considered in this paper is the generalized base-b hypercube that is an attractive variant of the well-known hypercube. The generalized base-b hypercube is superior to the hypercube in many criteria, such as diameter, connectivity, and fault diameter. In this paper, we study the panconnectivity and pancycle-connectivity of the generalized base-b hypercube. We show that a generalized base-b hypercube is panconnected for b ≥ 3. That is, for each pair of distinct vertices x and y of the n-dimensional generalized base-b hypercube GH(b, n) and for any integer l, where Dist(x, y) ≤ l ≤ N − 1, there exists a path of the length l joining x and y, where N is the order of the graph GH(b, n) and Dist(x, y) is the distance between x and y. We also show that a generalized base-b hypercube is pancycleconnected for b ≥ 3. That is, every two distinct vertices x and y of the graph GH(b, n) are contained by a cycle of every length ranging from the length of the smallest cycle that contains x and y to N .

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A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures

Furhad

Kim

2014

J Supercomput

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The m-pancycle-connectivity of a WK-Recursive network

Cited by 18 publications

References 24 publications

An interconnection architecture for network-on-chip systems

An interconnection architecture for network-on-chip systems

The panconnectivity and the pancycle-connectivity of the generalized base-b hypercube

A shortly connected mesh topology for high performance and energy efficient network-on-chip architectures

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