The LHCb Run Control System

Alessio, F.; Callot, O.; Cardoso, L. Granado; Franek, B.; Frank, M.; Garnier, Jean-Christophe; Gaspar, C.; Hervijnen, E. v.; Jacobsson, R.; Jost, B.; Neufeld, N.; Schwemmer, R.

doi:10.1109/rtc.2010.5750363

Cited by 4 publications

(1 citation statement)

References 2 publications

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“…While the TELL40 is responsible for the readout of the FE event fragments, the SODIN plays the role of readout supervisor, distributing the LHC clock, generating synchronous and asynchronous commands to the full readout system and dispatching event data to the event building stage. The SOL40 is an Interface Board that is responsible for interfacing both TFC (Timing and Fast Control) [5] and ECS (Experiment Control System) [6] with the FE boards. It relays timing and clock information sent by SODIN into the optical link to the FE, while also using the same data frame to give the ECS capabilities to both control and monitor the FE over the same link.…”

Section: Introductionmentioning

confidence: 99%

The New Version of the LHCb SOL40-SCA Core to Drive Front-End GBT-SCAs for the LHCb Upgrade

Barbosa¹,

Alessio²,

Gaspar³

2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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The LHCb experiment is currently engaged in an upgrade effort that will implement a triggerless 40 MHz readout system. The upgraded Front-End Electronics profit from the GBT chipset functionalities and bidirectional optical fibers for readout, control and synchronization. This paper describes the new version of the firmware core that transmits slow control information from the Control System to thousands of Front-End chips and discusses the implementation that expedites and makes the operation more versatile. The detailed architecture, original interaction with the software control system and integration within the LHCb upgraded architecture are described.

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Section: Introductionmentioning

confidence: 99%

The New Version of the LHCb SOL40-SCA Core to Drive Front-End GBT-SCAs for the LHCb Upgrade

Barbosa¹,

Alessio²,

Gaspar³

2018

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP-17)

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The LHCb vertex locator upgrade — the detector calibration overview

2022

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The Vertex Locator (VELO) is a silicon tracking detector in the spectrometer of the Large Hadron Collider beauty (LHCb) experiment. LHCb explores and investigates CP violation phenomena in b- and c- hadron decays and is one of the experiments operating on the Large Hadron Collider (LHC) at CERN. After run 1 and run 2 of LHC data taking (2011–2018), the LHCb detectors are being modernized within the LHCb upgrade I program. The upgrade aims to adjust the spectrometer to readout at full LHC 40 MHz frequency, which requires radical changes to the technologies currently used in LHCb. The hardware trigger is removed, and some of the detectors replaced. The VELO changes its tracking technology and silicon strips are replaced by 55 μm pitch silicon pixels. The readout chip for the VELO upgrade is the VeloPix ASIC. The number of readout channels increases to over 40 million, and the hottest ASIC is expected to produce the output data rate of 15 Gbit/s. New conditions challenge the software and the hardware side of the readout system and put special attention on the detector monitoring. This paper presents the upgraded VELO design and outlines the software aspects of the detector calibration in the upgrade I. An overview of the challenges foreseen for the upgrade II is given.

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