“…In the past, researchers attempted to eradicate variability in resistive switching behavior by device engineering, e.g. the introduction of an additional Al 2 O 3 layer [14], Germanium layer [15], T iOx layer [16] and other such techniques. The subject of variability and its causes is still a matter of intense research.…”
Intrinsic variability observed in resistive-switching devices (cycle-to-cycle and device-to-device) is widely recognised as a major hurdle for widespread adoption of Resistive RAM technology. While physics-based models have been developed to accurately reproduce the resistive-switching behaviour, reproducing the observed variability behavior of a specific RRAM has not been studied. Without a properly fitted variability in the model, the simulation error introduced at the device-level propagates through circuit-level to system-level simulations in an unpredictable manner. In this work, we propose an algorithm to fit a certain amount of variability to an existing physicsbased analytical model (Stanford-PKU model). The extent of variability exhibited by the device is fitted to the model in a manner agnostic to the cause of variability. Further, the model is modified to better reproduce the variations observed in a device. The model, fitted with variability can well reproduce cycle-tocycle, as well as device-to-device variations. The significance of integrating variability into RRAM models is underscored using a sensing example. Index Terms-Resistive RAM (RRAM), physics-based models, cycle-to-cycle variability, device-to-device variability, Stanford model, memristor, sense amplifier, resistive-switching, 1T-1R there cannot be a proper assessment of the functionality and yield of RRAM-based ICs, which will result in a series of expensive trial-and-errors. Pessimistic design approaches which allocate huge safety margins to accommodate variability are not recommended since they sacrifice design properties like energy, delay, and area. Consequently, there is an exigent RRAM models FEM DFT KMC Simulation speed Stanford-PKU model Classification based on abstraction levels Computational cost Physical detail Circuit µm 2-mm 2 Devicẽ 10 3 nm 3 Material few nm 3 Compact model Classification based on modeling approach Physical model (from first principles) Analytical Physics-based Black-box (measurement) Stanford-PKU model
“…In the past, researchers attempted to eradicate variability in resistive switching behavior by device engineering, e.g. the introduction of an additional Al 2 O 3 layer [14], Germanium layer [15], T iOx layer [16] and other such techniques. The subject of variability and its causes is still a matter of intense research.…”
Intrinsic variability observed in resistive-switching devices (cycle-to-cycle and device-to-device) is widely recognised as a major hurdle for widespread adoption of Resistive RAM technology. While physics-based models have been developed to accurately reproduce the resistive-switching behaviour, reproducing the observed variability behavior of a specific RRAM has not been studied. Without a properly fitted variability in the model, the simulation error introduced at the device-level propagates through circuit-level to system-level simulations in an unpredictable manner. In this work, we propose an algorithm to fit a certain amount of variability to an existing physicsbased analytical model (Stanford-PKU model). The extent of variability exhibited by the device is fitted to the model in a manner agnostic to the cause of variability. Further, the model is modified to better reproduce the variations observed in a device. The model, fitted with variability can well reproduce cycle-tocycle, as well as device-to-device variations. The significance of integrating variability into RRAM models is underscored using a sensing example. Index Terms-Resistive RAM (RRAM), physics-based models, cycle-to-cycle variability, device-to-device variability, Stanford model, memristor, sense amplifier, resistive-switching, 1T-1R there cannot be a proper assessment of the functionality and yield of RRAM-based ICs, which will result in a series of expensive trial-and-errors. Pessimistic design approaches which allocate huge safety margins to accommodate variability are not recommended since they sacrifice design properties like energy, delay, and area. Consequently, there is an exigent RRAM models FEM DFT KMC Simulation speed Stanford-PKU model Classification based on abstraction levels Computational cost Physical detail Circuit µm 2-mm 2 Devicẽ 10 3 nm 3 Material few nm 3 Compact model Classification based on modeling approach Physical model (from first principles) Analytical Physics-based Black-box (measurement) Stanford-PKU model
“…In this scenario, resistive-switching random access memories (ReRAMs), belonging to the wide family of memristor devices, have recently attracted great interest for their logic-in-memory capability , and their ability to emulate the synapse behavior. − A ReRAM cell is a two terminal electronic device whose memory properties are related to the retention of an internal resistance state, tunable by resistive switching between a high and a low resistance state (HRS, LRS) through the applied voltage stimuli. Among different ReRAM classes, oxide-based valence change memories (VCMs), consisting of simple structures in which a metal oxide layer (e.g., HfO 2 , TiO 2 , Ta 2 O 5 ) ,− is sandwiched between two asymmetric electrodes, show excellent properties in terms of high density integration, , sub-nanosecond operational speed, good memory retention, and low power consumption (≤0.1 pJ). , In VCM, the working principle behind resistance switching between HRS and LRS has been extensively studied by several works. − The phenomenon is related to the formation and rupture of an oxygen deficient conductive nanofilament (CNF) in the oxide layer by oxygen exchange at the insulator/electrode interface and O 2– ion migration under applied voltage. The SET process determines the transition from HRS to LRS due to CNF formation in correspondence to V set , while the RESET process is responsible for the opposite transition and the CNF is ruptured at V reset .…”
Resistive-switching
random access memory (ReRAM) technologies are
nowadays a good candidate to overcome the bottleneck of Von Neumann
architectures, taking advantage of their logic-in-memory capability
and the ability to mimic biological synapse behavior. Although it
has been proven that ReRAMs can memorize multibit information by the
storage of multiple internal resistance states, the precise control
of the multistates, their nonvolatility, and the cycle-to-cycle reliability
are still open challenges. In this study, the analog resistance modulation
of Pt/HfO2/Ti/TiN devices is obtained and studied in response
to different programming stimuli, linking the electrical response
to the internal dynamics of the ReRAM cells. The resistance modulation
during RESET operation is explained by the progressive dissolution
of the conducting filament, whose switching kinetics is inspected
in detail, describing the filament evolution during voltage sweep
measurements and under the effect of 1 μs pulses. Exploiting
the gradual nature of the RESET process, which is an intrinsic property
of our devices, a linear resistance modulation over the wide operating
window of 103 is obtained by negative pulse ramping. The
intermediate resistance states are characterized by small spatial
and temporal variability and stable retention over time. To explore
the synaptic long-term plasticity properties, the resistance variation
over 102 consecutive depression–potentiation cycles
is presented and up to 15 discrete distinguishable states are defined
through the evaluation of the maximum step-to-step variability. The
linear resistance modulation over a wide resistance window coupled
with the stable retention of intermediate states represents a fundamental
step forward to enhance HfO2 ReRAM performance in neuromorphic
applications.
Tungsten (W) is one of the most promising materials to be used in resistive random‐access memory electrodes due to its low work function and compatibility with semiconductors, which raises the possibility of device integration, scalability, and low power consumption. However, W has multiple oxidation states that affect device reliability, due to the formation of semistable oxides at the switching interface. W chemical interaction is modulated through the insertion of Al2O3 or Ti interfacial layers. The time‐dependent switching kinetics are investigated in transient Set/Reset operations. It is observed that a compact and stoichiometric atomic‐layer‐deposited Al2O3 barrier layer completely prevents W oxidation, resulting in a sharp current transient. The use of a sputtered Ti buffer layer allows a partial W oxidation, defining a tunable high‐resistance state by pulse rise time control. Notable improvements in endurance, power consumption, resistance state stabilization, and cycle‐to‐cycle and device‐to‐device variability are reported. Switching kinetics and conductive nanofilament evolution are studied in detail to understand the microscopic effect of the interface modifications. The tunability of multi‐HRS states by pulse timing control in Pt/HfO2/Ti/W is in the interest of network and brain‐inspired computing applications, adding a degree of freedom in the modulation of its resistance.
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