The ISPD98 circuit benchmark suite

Alpert, Charles J.

doi:10.1145/274535.274546

Cited by 273 publications

(229 citation statements)

References 11 publications

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“…The fingerprinting algorithm is implemented using the C++ language under Linux on a HP B7F41PA workstation with 3.3 GHz CPU and 4 GB of memory. We apply the CLIP FM partitioner [10] on the ISPD98 benchmark suite [11] for the evaluation. Table I shows the characteristics of the benchmark suite.…”

Section: Resultsmentioning

confidence: 99%

Circuit partitioning based fingerprinting method for IP protection

Nie

Sun

et al. 2013

IEICE Electron. Express

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Abstract:The continuously widening design productivity gap in the past few decades gives high incentives to counterfeiting ICs. Existing intellectual property (IP) protection schemes demand high overheads, and some techniques like watermarking do not facilitate tracing of illegal users. In this letter,we propose a novel fingerprinting method based on post-processing on circuit partitions. We evaluate our method on the ISPD98 benchmark suite. The experimental results demonstrate the effectiveness of the proposal. The fingerprinting design is distinct because the Hamming distance between fingerprinted IP designs is large enough to resist a collusion attack.

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Section: Resultsmentioning

confidence: 99%

Circuit partitioning based fingerprinting method for IP protection

Nie

Sun

et al. 2013

IEICE Electron. Express

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“…We have obtained results on two benchmark suites, the ACM/SIGDA and ISPD-98 [2] suites, for PROP and SHRINK-PROP, as well as FM and LA for comparisons. We also compare PROP and SHRINK-PROP to various other prior and current state-of-the-art partitioners like WINDOW, EIG1, MELO, PARABOLI, GFM, GMetis, and hMetis.…”

Section: Final Experimental Resultsmentioning

confidence: 99%

“…SHRINK-PROP obtains 6.2% better results TABLE IV CPU TIMES IN SECONDS FOR VARIOUS PARTITIONERS, FOR EACH CIRCUIT AND TOTAL TIMES OVER ALL CIRCUITS TABLE V ISPD-98 BENCHMARK CIRCUIT CHARACTERISTICS than PROP with a time-penalty factor of only two; it is, thus, also faster than most previous state-of-the-art techniques. Table V gives the characteristics of the 18 circuits in the ISPD-98 benchmark suite [2]. These circuits range from medium size (more than 10K nodes and nets, and 50K pins) to very large (more than 200K nodes and nets, and 800K pins).…”

Section: A Acm/sigda Benchmarks 1) Cutsize Resultsmentioning

confidence: 99%

“…One is that, since there are no certainties in node moves, it seems reasonable to establish a maximum probability and a minimum probability within which interval all node probabilities lie. 2 The second caveat is to establish upper and lower gain thresholds and such that all nodes with gains greater than or equal to will get probability while those with gains lower than will get probability The rationale for establishing thresholds is that nodes with high gains, say, greater than 2, will be moved to the other subset with very high likelihood, and those will very low gains, say less than -1, will most likely not be actually moved in the current pass. Thus, and should replace and respectively, in the above probability functions.…”

Section: Computing Node Probabilitiesmentioning

confidence: 99%

“…1(b) shows the initial gains and probabilities for each node; note that the node probabilities are consistent with a monotonically increasing probability function. We assume for simplicity of exposition that for each net to in the cutset, their terms are equal; thus, the difference in the node gains s will only depend on their 2 Actually, it is not unreasonable to have p = 1; but p needs to be greater than 0.…”

Section: An Examplementioning

confidence: 99%

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A probability-based approach to VLSI circuit partitioning

Dutt¹,

Deng²

33rd Design Automation Conference Proceedings, 1996

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Abstract-Iterative-improvement two-way min-cut partitioning is an important phase in most circuit placement tools, and finds use in many other computer-aided design (CAD) applications. Most iterative improvement techniques for circuit netlists like the Fiduccia-Mattheyses (FM) method compute the gains of nodes using local netlist information that is only concerned with the immediate improvement in the cutset. This can lead to misleading gain information. Krishnamurthy suggested a lookahead (LA) gain calculation method to ameliorate this situation; however, as we show, it leaves room for improvement. We present here a probabilistic gain computation approach called probabilistic partitioner (PROP) that is capable of capturing the future implications of moving a node at the current time. We also propose an extended algorithm SHRINK-PROP that increases the probability of removing recently "perturbed" nets (nets whose nodes have been moved for the first time) from the cutset. Experimental results on medium-to large-size ACM/SIGDA benchmark circuits show that PROP and SHRINK-PROP outperform previous iterative-improvement methods like FM (by about 30% and 37%, respectively) and LA (by about 27% and 34%, respectively). Both PROP and SHRINK-PROP also obtain much better cutsizes than many recent state-of-the-art partitioners like EIG1, WINDOW, MELO, PARABOLI, GFM and GMetis (by 4.5% to 67%). Our empirical timing results reveal that PROP is appreciably faster than most recent techniques. We also obtain results on the more recent ISPD-98 benchmark suite that show similar substantial mincut improvements by PROP and SHRINK-PROP over FM (24% and 31%, respectively). It is also noteworthy that SHRINK-PROP's results are within 2.5% of those obtained by hMetis, one of the best multilevel partitioners. However, the multilevel paradigm is orthogonal to SHRINK-PROP. Further, since it is a "flat" partitioner, it has advantages over hMetis in partition-driven placement applications.Index Terms-Clustering effect, iterative-improvement, min-cut partitioning, probabilistic gain, VLSI circuit.

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Multiscale Optimization in VLSI Physical Design Automation

Chan

Cong

Shinnerl

et al.

Multiscale Optimization Methods and Applications

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Summary. The enormous size and complexity of current and future integrated circuits (IC's) presents a host of challenging global, combinatorial optimization problems. As IC's enter the nanometer scale, there is increased demand for scalable and adaptable algorithms for VLSI physical design: the transformation of a logicaltemporal circuit specification into a spatially explicit one. There are several key problems in physical design. We review recent advances in multiscale algorithms for three of them: partitioning, placement, and routing.

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The ISPD98 circuit benchmark suite

Cited by 273 publications

References 11 publications

Circuit partitioning based fingerprinting method for IP protection

Circuit partitioning based fingerprinting method for IP protection

A probability-based approach to VLSI circuit partitioning

Multiscale Optimization in VLSI Physical Design Automation

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