The ISPD-2012 discrete cell sizing contest and benchmark suite

Özdal, Mustafa; Amin, Chirayu; Ayupov, Andrey; Burns, Steven; Wilke, Gustavo; Zhuo, Cheng

doi:10.1145/2160916.2160950

Cited by 77 publications

(48 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Prior approaches have at most considered one or two terms accurately [16], and/or do not differentiate between the duty cycle with respect to switching and leakage energy weights, leaving many approaches to be either dynamic or leakage power-centric. For example, the state-of-the-art gate sizing contest considers only nominal leakage power [5]. Our technique minimizes total energy, such that both the switching and leakage energy components are accurately accounted for in accordance to their usage or duty cycle.…”

Section: Related Workmentioning

confidence: 99%

“…Gate sizing has been extensively studied over the past three decades [2][3][4][5] and several approaches have been proposed. Previous approaches, however, do not consider optimization uncertainty factors, such as switching activity (SA) and the impact of input vector control leakage (IVC), which greatly impact the overall optimization strategy.…”

Section: Introductionmentioning

confidence: 99%

“…Accounting for accurate gate and interconnect delay and its dependencies on capacitive load slew are often ignored [5]. Additionally, nominal gate switching activity and/or average gate leakage are generally assumed in previous works limiting the potential improvements by accounting for realistic operating conditions.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Gate Sizing Under Uncertainty

Conos

Meguerdichian

Potkonjak

2015

IFIP Advances in Information and Communication Technology

View full text Add to dashboard Cite

Abstract. We present a gate sizing approach to efficiently utilize gate switching activity (SA) and gate input vector control leakage (IVC) uncertainty factors in the objective function in order enable more efficient power and speed yield tradeoffs. Our algorithm conducts iterative gate freezing and unlocking with cut-based search for the most beneficial gate sizes under delay constraints. In an iterative flow, we interchangeably conduct gate sizing and IVC refinement to adapt to new circuit configurations. We evaluate our approach on benchmarks in 45 nm technology and demonstrate up to 62% (29% avg.) energy savings compared to a traditional objective function that does not consider SA and IVC. We further adapt our approach to optimize yield objectives by addressing processing variation (PV). Significant improvements were achieved under identical timing yield targets of up to 84% max (55% avg.) and 74% max (25% avg.) mean-power savings for selected ISCAS-85 and ITC-99 benchmarks, respectively.

show abstract

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Gate Sizing Under Uncertainty

Conos

Meguerdichian

Potkonjak

2015

IFIP Advances in Information and Communication Technology

View full text Add to dashboard Cite

show abstract

“…ISPD-2012 and 2013 Gate Sizing Contests [17,18] have dramatically changed the landscape of research in the field. To this end, the benchmarking infrastructure developed by Intel researchers does not have academic precedents in terms of…”

Section: Comparisons To Prior Researchmentioning

confidence: 99%

“…To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. For the ISPD-2012 Gate Sizing Contest [17], Intel researchers prepared several large gate sizing benchmarks to empirically compare competing leakage power optimizations. The contest methodology requires the use of Synopsys PrimeTime [29].…”

Section: Introductionmentioning

confidence: 99%

High-performance gate sizing with a signoff timer

Kahng

Kang

Lee

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

Process and device scaling in late-CMOS technologies highlight leakage power as a critical challenge for the semiconductor industry. Careful gate sizing and V th -swapping can reduce leakage, but prior optimizations based on convex or dynamic programming (i) are often based on unrealistic assumptions about circuit delay and slew propagation, (ii) fail to handle practical design rules such as transition time or load upper bounds, and (iii) do not scale well to input complexities when full extracted parasitics are available. Seeing substantial opportunities for improvement, we present a multithreaded, stochastic optimization (Trident2.0) for gate sizing and V th assignment to minimize leakage power subject to capacitance, slew and timing constraints. Scalability and high performance of Trident2.0 are validated on ISPD-2013 Gate Sizing Contest benchmarks.

show abstract