“…Main contributions: In this paper we are thus extending the evaluation of the IDM to additional place & routed circuits: For an OR Loop, an SR Latch and a ripple-carry Adder (i) analog and digital simulations are run, (ii) the achieved results are evaluated and finally (iii) the introduced overhead is determined. Our analyses (1) confirm the simple applicability of the IDM stated in [4], (2) show a high correlation between IDM and analog simulation results and (3) reveal major shortcomings of the approaches that are currently in use. The realistic behavioral description, however, also leads to a significant overhead in the simulation time of up to 250%.…”
Section: Introductionsupporting
confidence: 72%
“…For example the quick increase on S 4 in relation to S 3 is not well depicted. Possible causes are inaccurate delay values extracted from the design (as reported in [4]) or the still nonoptimal description of multi-input gates. Nonetheless, due to its accurate pulse width degradation coverage, the IDM is able to provide overall realistic results.…”
Section: Addermentioning
confidence: 99%
“…Although several approaches are currently available (see Section II), Függer et al [3] revealed, that solely the Involution Delay Model (IDM) is able to predict the behavior of a circuit solving the short pulse filtration problem. Recently Öhlinger et al [4] practically applied the IDM to basic circuits, however, primarily to evaluate the accuracy of their introduced simulation framework. Consequently little is known about the behavioral coverage and performance of the IDM in realistic setups.…”
Section: Introductionmentioning
confidence: 99%
“…Albeit there is a distinguished simulation tool for DDM [11] available, it is shipped as a separate executable, making it demanding to integrate the simulation into an existing design flow. To circumvent this problem for the IDM, Öhlinger et al [4] developed the InvTool, whose VHDL procedures simply have to be linked and thus enforce no changes on the established work flow.…”
Simulation on small circuits reveal, that the commonly used methods fail
to provide a comprehensive picture of the possible behavior. The
Involution Delay Model, however, manages to fill this gap at a cost of
increased simulation time.
“…Main contributions: In this paper we are thus extending the evaluation of the IDM to additional place & routed circuits: For an OR Loop, an SR Latch and a ripple-carry Adder (i) analog and digital simulations are run, (ii) the achieved results are evaluated and finally (iii) the introduced overhead is determined. Our analyses (1) confirm the simple applicability of the IDM stated in [4], (2) show a high correlation between IDM and analog simulation results and (3) reveal major shortcomings of the approaches that are currently in use. The realistic behavioral description, however, also leads to a significant overhead in the simulation time of up to 250%.…”
Section: Introductionsupporting
confidence: 72%
“…For example the quick increase on S 4 in relation to S 3 is not well depicted. Possible causes are inaccurate delay values extracted from the design (as reported in [4]) or the still nonoptimal description of multi-input gates. Nonetheless, due to its accurate pulse width degradation coverage, the IDM is able to provide overall realistic results.…”
Section: Addermentioning
confidence: 99%
“…Although several approaches are currently available (see Section II), Függer et al [3] revealed, that solely the Involution Delay Model (IDM) is able to predict the behavior of a circuit solving the short pulse filtration problem. Recently Öhlinger et al [4] practically applied the IDM to basic circuits, however, primarily to evaluate the accuracy of their introduced simulation framework. Consequently little is known about the behavioral coverage and performance of the IDM in realistic setups.…”
Section: Introductionmentioning
confidence: 99%
“…Albeit there is a distinguished simulation tool for DDM [11] available, it is shipped as a separate executable, making it demanding to integrate the simulation into an existing design flow. To circumvent this problem for the IDM, Öhlinger et al [4] developed the InvTool, whose VHDL procedures simply have to be linked and thus enforce no changes on the established work flow.…”
Simulation on small circuits reveal, that the commonly used methods fail
to provide a comprehensive picture of the possible behavior. The
Involution Delay Model, however, manages to fill this gap at a cost of
increased simulation time.
“…Függer et al [5] thus introduced the Involution Delay Model (IDM), with the distinguishing property that the delay functions for rising ( ↑ ) and falling ( ↓ ) transitions form an involution, i.e., − ↑ (− ↓ ( )) = , which enables faithful short pulse propagation. The Involution Tool [15], a simulation framework utilizing a digital simulation suite, has been used to confirm the models accuracy.…”
We introduce the Composable Involution Delay Model (CIDM) for fast and accurate digital simulation. It is based on the Involution Delay Model (IDM) [Függer et al., IEEE TCAD 2020], which has been shown to be the only existing candidate model for faithful glitch propagation. The IDM, however, has shortcomings that limit its applicability. Our CIDM thus reduces the characterization effort by allowing independent discretization thresholds, improves composability and increases the modeling power by exposing canceled pulse trains at the gate interconnect. We formally show that, despite these improvements, the CIDM still retains the IDM's faithfulness.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.