The Integration of SystemC and Hardware-Assisted Verification

Ramaswamy, Ramaswamy; Tessier, Russell

doi:10.1007/3-540-46117-5_103

Cited by 5 publications

(3 citation statements)

References 2 publications

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“…The communication between real devices and virtual models can range from pin level [31]- [33] to transaction level [30], [34]- [37]. Pinlevel approaches offer great flexibility, as any communication protocol can be modeled on top of pin-level when necessary.…”

Section: Integrating Real and Virtual Environmentsmentioning

confidence: 99%

A Heterogeneous Simulation and Modeling Framework for Automation Systems

Fennibay¹,

Yurdakul

Şen

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Recently, new technologies have emerged in industrial automation platforms. A rapid modeling and simulation environment is required to integrate these new technologies with existing devices and platforms to reduce the design effort and time to market. System-level modeling is a popular design technique that provides early simulation, verification, and architectural exploration. However, integration of real devices with system models is quite challenging due to synchronization and hard real-time constraints in industrial automation. SystemC is the most commonly used system-level language in hardware-software codesign. However, SystemC lacks interfaces for the integration of system (virtual) models with real (physical) devices. We introduce the hybrid channel concept to clearly define the integration interface. Hybrid channel incorporates both real-tovirtual and virtual-to-real communication functions by solving synchronization issues while satisfying the real-time constraints.We successfully demonstrated the usability of our framework in industrial systems that utilize BACNet and Ethernet. We also developed a mathematical model that correctly estimates the results of our experiments. To the best of our knowledge, this is the first framework and mathematical model for SystemC in industrial automation domain.

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Section: Integrating Real and Virtual Environmentsmentioning

confidence: 99%

A Heterogeneous Simulation and Modeling Framework for Automation Systems

Fennibay¹,

Yurdakul

Şen

2012

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…The communication between real and virtual subsystems can range from pin-level to transactionlevel. The works in [10]- [14] are examples of the pin-level communication, and the works in [9], [15]- [18] are examples of the transaction-level communication. It should be noted that not all approaches address the hardware-in-the-loop method; [11], [15], [17], [18] propose connecting models to real subsystems only to increase the overall execution performance by using the real subsystems as coprocessors.…”

Section: B Integration Of Different Environmentsmentioning

confidence: 99%

Introducing Hardware-in-Loop Concept to the Hardware/Software Co-design of Real-time Embedded Systems

Fennibay

Yurdakul

Şen

2010

2010 10th IEEE International Conference on Computer and Information Technology

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Abstract-As the need for embedded systems to interact with other systems is growing fast, we see great opportunities in introducing the hardware-in-the-loop technique to the field of hardware/software co-design of embedded systems. This technique reduces the need to develop models for existing hardware and increases the accuracy of the overall system. This work is especially important now that complexity and time-to-market constraints demand early simulation, verification, and architectural exploration of systems. We introduce the hardware-in-the loop technique to the field of hardware/software co-design of industrial embedded systems using SystemC as the modeling environment. We conceptualize the hybrid channel to clearly define the communication between real and virtual (modeled) subsystems. We patch the SystemC kernel for hard real-time execution and we improve the underlying operating system to guarantee an upper bound for the overall system latency. We have performed tests to measure the performance of our method in terms of response time and determinism. We have achieved a stable operating frequency of 10 KHz and an I/O performance of sub-millisecond round-trip time over Ethernet. Moreover we have developed a non-timed transaction-level model of a BACnet Broadcast Management Device (BBMD) and connected it with real devices to see our method's performance in a real-life environment. Our model outperformed the competing real system up to 80 times in maximum response time. We deem the results very promising for the future of our method.

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“…In [1] and [17], the authors tackle automatic communication refinement, and Kogel et al [11] address virtual architecture mapping using a generic bus model. Fummi et al [3] and Ramaswamy et al [14] show application-specific techniques for HW-assisted verification with SystemC. However, all of these approaches do not provide generic solutions for TLM-to-RTL communication synthesis.…”

Section: Figure 1 Complex Multiprocessor Socmentioning

confidence: 99%

TRAIN: A Virtual Transaction Layer Architecture for TLM-based HW/SW Codesign of Synthesizable MPSoC

Klingauf

Gädke

Giinzel

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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Our concept of a virtual transaction layer (VTL) architecture allows to directly map transaction-level communication channels onto a synthesizable multiprocessor SoC implementation. The VTL is above the physical MPSoC communication architecture, acting as a hardware abstraction layer for both HW and SW components. TLM channels are represented by virtual channels which efficiently route transactions between SW and HW entities through the on-chip communication network with respect to quality-of-service and realtime requirements. The goal is to methodically simplify MPSoC design by systematic HW/SW interface abstraction, thus enabling early SW verification, rapid prototyping and fast exploration of critical design issues. With TRAIN, we present our implementation of such a VTL architecture for Virtex-II Pro and PowerPC and illustrate its efficiency by experimentation. end, a flexible and scalable HW/SW communication architecture is required which from the programmer's point of view fully retains all TLM channels as virtual channels in the final system implementation. The key features that such an architecture should provide are:Flexibility: The hardware part of the architecture should be highly flexible and scalable, enabling each processor core to be connected to an arbitrary number of on-chip communication networks. Performance:The HW/SW interface should deliver highest possible data transfer rates according to the underlying communication subsystems. Adaptability:The VTL should be highly retargetable, rendering any re-engineering of MPSoC components unnecessary. For software components, TLM channel interface method calls such as put and get should be transparently mapped to the HW/SW interface. Hardware components should be accessible independently from their communication protocol.Configurability: Each TLM channel of the high-level system model should be represented by a virtual communication channel in the implementation model. Virtual

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The Integration of SystemC and Hardware-Assisted Verification

Cited by 5 publications

References 2 publications

A Heterogeneous Simulation and Modeling Framework for Automation Systems

A Heterogeneous Simulation and Modeling Framework for Automation Systems

Introducing Hardware-in-Loop Concept to the Hardware/Software Co-design of Real-time Embedded Systems

TRAIN: A Virtual Transaction Layer Architecture for TLM-based HW/SW Codesign of Synthesizable MPSoC

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