The Integration of Sub-10 nm Gate Oxide on MoS2 with Ultra Low Leakage and Enhanced Mobility

Abstract

The integration of ultra-thin gate oxide, especially at sub-10 nm region, is one of the principle problems in MoS2 based transistors. In this work, we demonstrate sub-10 nm uniform deposition of Al2O3 on MoS2 basal plane by applying ultra-low energy remote oxygen plasma pretreatment prior to atomic layer deposition. It is demonstrated that oxygen species in ultra-low energy plasma are physically adsorbed on MoS2 surfaces without making the flakes oxidized, and is capable of benefiting the mobility of MoS2 flake. Based on this method, top-gated MoS2 transistor with ultrathin Al2O3 dielectric is fabricated. With 6.6 nm Al2O3 as gate dielectric, the device shows gate leakage about 0.1 pA/μm2 at 4.5 MV/cm which is much lower than previous reports. Besides, the top-gated device shows great on/off ratio of over 108, subthreshold swing (SS) of 101 mV/dec and a mobility of 28 cm2/Vs. With further investigations and careful optimizations, this method can play an important role in future nanoelectronics.

Fabrication and tribological characterization of laser textured boron cast iron surfaces

“…For the untextured surfaces, the peak at 225.78 eV in Fig. 14 (c [38], indicating that some MoS 2 remained on the surfaces as a result of deformation. This seems to be contrast to the Raman spectra in Fig.10b [39], suggesting some oxide components in the tribo-film are formed.…”

Progress in Contact, Doping and Mobility Engineering of MoS2: An Atomically Thin 2D Semiconductor

“…as well as nanometer scalability (to reduce their effective oxide thickness "EOT" for enhanced gate control over the MoS 2 channel). The interested reader is directed to various literature reports for further reading on these topics [317][318][319][320][321][322][323][324][325][326][327][328][329][330][331][332][333]. The focus of the following discussion is on the influence of dielectric engineering on important device parameters, such as doping, carrier mobility, ON-currents and contact resistance, and how dielectric engineering can be used to help enhance the performance of MoS 2 -based devices.…”

Recent progress in devices and circuits based on wafer-scale transition metal dichalcogenides

“…The electrical transport in TMD based FETs are significantly influenced by scattering sources including charge impurities, interfacial traps, and defects generated during the ALD process, leading to the degradation of electrical performance. Various technical efforts have been demonstrated to deposit homogeneous high-k dielectrics, such as the insertion of a seeding layer [85], remote plasma treatment [86], and ultraviolet-ozone exposure [87]. Liao et al [85] reported the deposition of Y 2 O 3 on MoS 2 as a buffer layer before the growth of HfO 2 dielectric.…”