The instruction systolic array and its relation to other models of parallel computers

Kunde, Manfred; Lang, Hans-Werner; Schimmler, Manfred; Schmeck, Hartmut; Schröder, Heiko

doi:10.1016/0167-8191(88)90095-6

Cited by 29 publications

(12 citation statements)

References 3 publications

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“…The boundary cells may impose no delay or delay of one IPS, depending on the type of operation they perform. The type of operation of the boundary cells may be defined by a control instruction accompanying the data input [6], [12]. For example, in the cases of the mmips computation the control signals required are [3] The data and control sequences may be different in the row and column inputs of the systolic array (i.e.…”

Section: Parallel Implementation Of Iterative Methodsmentioning

confidence: 99%

Iterative matrix inversion on a systolic array: a case of algorithm integration

Margaritis

Evans

1994

International Journal of Computer Mathematics

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This paper describes the implementation of the Pan-Reif iterative algorithm for matrix inversion on the re-usable systolic processor array for matrix multiplication. The calculation ofinitial approximations, matrix norms and matrix transposition are implemented on the same processor array. Further the inversion of several special matrices is also discussed. All phases of the iterative algorithm are integrated so that they can be executed without any communication with a host system. The parallel algorithms and the systolic designs were implemented using Occam.

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Section: Parallel Implementation Of Iterative Methodsmentioning

confidence: 99%

Iterative matrix inversion on a systolic array: a case of algorithm integration

Margaritis

Evans

1994

International Journal of Computer Mathematics

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“…. ; X½4: Here, X [4] contains the exponent of the double, the sign, the kind of representation (absolute value/sign or 2-complement), and information about possible special cases (infinity, zero, NaN ¼ not a number). X[0] to X [3] contain the significant (mantissa) of the double, extended to 64 bits.…”

Section: Internal Floating Point Formatmentioning

confidence: 99%

A bit-serial floating-point unit for a massively parallel system on a chip

Schimmler¹,

Schmidt

Lang

2004

Parallel Algorithms and Applications

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This paper presents the design of a new bit-serial floating-point unit (FPU). It has been developed for the processors of the instruction systolic array (ISA) parallel computer model. In contrast to conventional bit-parallel FPUs the bitserial approach requires a different data format. Our FPU uses an IEEE compliant internal floating-point format that allows a fast least significant bit (LSB)-first arithmetic and can be efficiently implemented in hardware.

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“…In (Lang, 1985) the instruction systolic array (ISA) has been suggested as a new architecture for parallel computation which meets the requirements of VLSI and be capable of efficiently executing a large variety of parallel algorithms.…”

Section: The Instruction Systolic Array (Isa)mentioning

confidence: 99%