The Implementation of Fractional Pixel ME in H.264 Video Encoder

Abstract

This paper first introduce the H.264 video codec standard briefly, then analyze the inter-frame motion estimation in H.264. After that we propose an optimaized algorithm and the corresponding architecture. A pipeline-architecture was proposed with scaled searching algorithm based on the analysis to the previous work and the consideration of the system requirement between chip area and performance. A pipelined architecture with two 1-dimension interpolation for fractional pixe ME was proposed to meet the needs of SHD(2160P) video encoding, resulting in lower complexity and more throughout. Synthesized with Charted 0.13μm process, the design consumed 174.3K logic gates, with peak frequency of about 200MHz, and consumed less than 20mW at the power supply of 1.20V.