The impact of technology scaling on lifetime reliability

Srinivasan, Jayanth; Adve, Sarita V.; Bose, Pradip; Rivers, Jude A.

doi:10.1109/dsn.2004.1311888

Cited by 448 publications

(282 citation statements)

References 9 publications

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“…Coming up with a resource-efficient scheduling algorithm to mask job errors is important since job errors are more frequent due to the rising trend of non-permanent hardware faults in computer electronics, as it was pointed out by Baumann (2005), Srinivasan et al (2004), and Borkar (2005). This paper considers tolerating both non-permanent and permanent faults using global scheduling that does not need any (offline) allocation of backups, which can reduce the number of required cores.…”

Section: Fault-tolerant Real-time Schedulingmentioning

confidence: 99%

Real-time scheduling algorithm for safety-critical systems on faulty multicore environments

Pathan

2016

Real-Time Syst

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An algorithm (called FTM) for scheduling of real-time sporadic tasks on a multicore platform is proposed. Each task has a deadline by which it must complete its non-erroneous execution. The FTM algorithm executes backups in order to recover from errors caused by non-permanent and permanent hardware faults. The worst-case schedulability analysis of FTM algorithm is presented considering an applicationlevel error model, which is independent of the stochastic behavior of the underlying hardware-level fault model. Then, the stochastic behavior of hardware-level fault model is plugged in to the analysis to derive the probability of meeting all the deadlines. Such probabilistic guarantee is the level of assurance (i.e., reliability) regarding the correct functional and timing behaviors of the system. One of the salient features of FTM algorithm is that it executes some backups in active redundancy to exploit the parallel multicore architecture while other backups passively to avoid unnecessary execution of too many active backups. This paper also proposes a scheme to determine for each task the number of backups that should run in active redundancy in order to increase the probability of meeting all the deadlines. The effectiveness of the proposed approach is demonstrated using an example application.

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Section: Fault-tolerant Real-time Schedulingmentioning

confidence: 99%

Real-time scheduling algorithm for safety-critical systems on faulty multicore environments

Pathan

2016

Real-Time Syst

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“…There is no straightforward method of deriving a closed-form expression for the failure rate of a microprocessor composed of numerous components for which lognormal fault process models are used. Therefore, some microprocessor reliability estimation work assumes exponential fault processes, which may be inaccurate, while other work uses Monte Carlo simulation [17] or techniques based on statistical curve fitting, each of which may be slow. At present, efficient and accurate system-level lifetime reliability estimation is a goal that remains just slightly out of grasp, but toward which research is rapidly progressing.…”

Section: A Modeling Permanent Power and Temperature Related Faultsmentioning

confidence: 99%

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

et al. 2007

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Power is the source of the greatest problems facing microprocessor designers. High-power processors rapidly deplete battery energy. Rapid changes in power consumption result in on-chip voltage fluctuations that bring transient errors. High spatial and temporal power densities bring high temperatures, which result in decreased lifetime reliability. High temperatures also increase leakage power consumption, thereby closing a self-reinforcing powertemperature feedback loop. The effects of increasing power consumption, power variation, and power density are expensive and distasteful. The wages of power are bulky short-lived batteries, huge heatsinks, large on-die capacitors, high server electric bills, and unreliable microprocessors. The only alternative is optimizing microprocessor power consumption, temperature, and reliability. However, this depends on accurate modeling and rapid analysis of properties that span different disciplines and levels, from device physics, to numerical methods, to microarchitectural design. This article surveys the most important problems brought directly and indirectly by power consumption, indicates the relationships among them, explains recent methods of efficiently modeling them, and indicates promising directions in the ongoing fight against power.

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“…However, challenges in producing reliable components in these extremely dense technologies are growing, with many device experts warning that continued scaling will inevitably lead to future generations of silicon technology being much less reliable than present ones [3,32]. Processors manufactured in future technologies will likely experience failures in the field due to silicon defects occurring during system operation.…”

Section: Introductionmentioning

confidence: 99%

Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation

Constantinides

Mutlu²,

Austin

et al. 2007

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)

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As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future processor systems, unless new online techniques become available to detect and to tolerate them while preserving the integrity of software applications running on the system. This paper proposes a new, software-based, defect detection and diagnosis technique. We introduce a novel set of instructions, called Access-Control Extension (ACE), that can access and control the microprocessor's internal state. Special firmware periodically suspends microprocessor execution and uses the ACE instructions to run directed tests on the hardware. When a hardware defect is present, these tests can diagnose and locate it, and then activate system repair through resource reconfiguration. The software nature of our framework makes it flexible: testing techniques can be modified/upgraded in the field to trade off performance with reliability without requiring any change to the hardware.We evaluated our technique on a commercial chip-multiprocessor based on Sun's Niagara and found that it can provide very high coverage, with 99.22% of all silicon defects detected. Moreover, our results show that the average performance overhead of softwarebased testing is only 5.5%. Based on a detailed RTL-level implementation of our technique, we find its area overhead to be quite modest, with only a 5.8% increase in total chip area.

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The impact of technology scaling on lifetime reliability

Cited by 448 publications

References 9 publications

Real-time scheduling algorithm for safety-critical systems on faulty multicore environments

Real-time scheduling algorithm for safety-critical systems on faulty multicore environments

Power, Thermal, and Reliability Modeling in Nanometer-Scale Microprocessors

Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation

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