The impact of sub monolayers of HfO/sub 2/ on the device performance of high-k based transistors [MOSFETs]

Ragnarsson, Lars‐Åke; Pantisano, L.; Kaushik, V.; Saito, Shinichi; Shimamoto, Yasuhiro; Gendt, Stefan De; Heyns, Marc

doi:10.1109/iedm.2003.1269172

Cited by 42 publications

(46 citation statements)

References 2 publications

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“…These experimental observations suggest that bringing the high-k layer closer to the Si-SiO 2 interface enhances the 1/f noise in both gate and drain currents. Moreover, the enhanced 1/f drain noise due to mobility fluctuations is consistent with the lower mobility values observed in high-k gate stacks with lower IL thickness [26], [27].…”

Section: B Impact Of Ilsupporting

confidence: 69%

$1/f$ Noise in Drain and Gate Current of MOSFETs With High-$k$ Gate Stacks

Magnone

Crupi

Giusi

et al. 2009

IEEE Trans. Device Mater. Relib.

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115

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Abstract-In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain-and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.Index Terms-Drain noise, gate noise, high-k dielectric, MOSFET, 1/f noise.

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Section: B Impact Of Ilsupporting

confidence: 69%

$1/f$ Noise in Drain and Gate Current of MOSFETs With High-$k$ Gate Stacks

Magnone

Crupi

Giusi

et al. 2009

IEEE Trans. Device Mater. Relib.

Self Cite

115

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“…The degradation of the mobility in presence of high-k oxide has been observed and studied by many authors. This degradation is attributed to scattering mechanisms such as remote Coulomb [6,7,26,27], remote phonon [28] or remote surface roughness scattering [29].…”

Section: Influence Of the Il Eotmentioning

confidence: 99%

“…Thanks to an excellent electrostatic control and transport properties, this architecture is suitable to reach ITRS requirements for 28 nm technology node and beyond [4].The threshold voltage can be easily adjusted by applying back biases (VB) and it has recently been demonstrated that the mobility can be enhanced in the forward regime (VB > 0 V for nMOS and VB < 0 V for pMOS) [5]. However, the presence of high-k dielectrics can induce mobility degradations when the Interfacial Layer (IL) Equivalent Oxide Thickness (EOT) is decreased [6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility

et al. 2013

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scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility. Journal of Computational Electronics, Springer Verlag, 2013, 12, pp.675-684. 10.1007 Multi-scale analysis of the mobility in high-k UTBB-FDSOI Devices and comparison to split-CV measurements. Abstract-A rigorous study of the mobility in high-k metal gate Ultra-Thin Body and Box Fully Depleted SOI (UTBB-FDSOI) devices is done by means of split C-V measurements and advanced simulations. Measurements have been performed for various Interfacial Layer (IL)Equivalent Oxide Thickness (EOT) allowing an investigation of the physical mechanisms responsible for the mobility degradation at high-k/IL interface. The impact of the back bias on transport properties is investigated and mobility enhancement in the forward regime (back gate inversion) is demonstrated. A multi-scale simulation approach is performed and we compared simulated mobility using quantum Non-Equilibrium Green's Functions (NEGF) to semi-classical solvers results using the Kubo Greenwood (KG) approach. We demonstrated good correlations between these solvers comparing phonon and remote Coulomb-limited mobility. However, a clear overestimation of the surface roughnesslimited mobility determined using semi-classical solvers is shown compared to NEGF results. These advanced solvers have been used to reproduce mobility measurements allowing us to calibrate Technology computer aided design (TCAD) mobility models.

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“…Esto causa que la movilidad de los MOS-FET con estos materiales aumente y es lógico pensar que se alcanza un mayor g m,max cuando µ también ha aumentado [9]. Esto en conceptos físicos significa que el transistor maximiza su entrega de corriente a la salida cuando el canal ha alcanzado la mayor cantidad de portadores moviéndose a mayor velocidad a través de su red cristalina.…”

Section: Característica I-vunclassified

Caracterización eléctrica de nano-MOSFETs en tecnología SOI

Artieda

Trojman

Crupi

et al. 2012

Av. Cienc. Ing. (Quito)

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This paper reports about the extensive electrical characterization, with low distortion and greater reliability, of MOSFET devices at nanometric scales with ultra thin Fully Depleted (FD) type architecture on Silicon-On-Insulator (SOI) technology to reduce the short channel effects. The parameters of nMOS type devices of 10x1 µm 2 gate dimensions with conventional dielectric (SiON) and alternative high-k dielectric (HfO2) are compared. The extracted parameters are: equivalent oxide thickness (EOT), threshold voltage (VT ) as a function of the SOI body voltage (VB), transconductance (gm), maximum transconductance (gm,max) and its corresponding relation with mobility. The objective is to find if the classic electrical characterization methodology can be applied to the new ultra thin devices overcoming the challenges and physical difficulties imposed by the SOI technology and to demonstrate if the ultra thin devices behavior is similar to conventional MOSFETs. The semiconductor devices analyzed were provided by the IMEC consortium in Belgium and have been characterized in the new nanoelectronics laboratory at Universidad San Francisco de Quito (USFQ) in Ecuador.Keywords. Electrical characterization, MOSFET, nMOS, nanoelectronics, FD architecture, SOI technology, conventional dielectric SiON, high-k dielectric HfO2, EOT, threshold voltage (VT ), transconductance (gm). ResumenEn esta investigación se reporta sobre la extensa caracterización eléctrica realizada, con poca distorsión y mayor fiabilidad, a dispositivos MOSFET de tamaño nanométrico con arquitectura ultra delgada tipo Fully Depleted (FD) en tecnología Silicon-On-Insulator (SOI) para reducir los efectos de canal corto. Se comparan los parámetros de dispositivos tipo nMOS, con tamaño de compuerta 10x1 µm 2 , con dieléctrico convencional (SiON) y dieléctrico alternativo de alto k (HfO2). Los parámetros que se extraen son: espesor equivalente de óxido (EOT), voltaje umbral (VT ) en función del voltaje de cuerpo SOI (VB), transconductancia (gm), pico de transconductancia (gm,max) y su relación con la movilidad. El objetivo es encontrar si los métodos de caracterización eléctrica clásicos pueden ser aplicables para estos nuevos dispositivos superando los retos y dificultades físicas que impone la tecnología de construcción SOI y demostrar si su funcionamiento es como el de los MOSFET convencionales. Los dispositivos semiconductores analizados fueron provistos por el consorcio IMEC en Bélgica y han sido caracterizados en el nuevo laboratorio de nanoelectrónica de la Universidad San Francisco de Quito (USFQ) en Ecuador.Palabras Clave. Caracterización eléctrica, MOSFET, nMOS, nanoelectrónica, arquitectura FD, tecnología SOI, dieléctrico convencional SiON, dieléctrico de alto k HfO2, EOT, voltaje umbral (VT ), transconductancia (gm). IntroducciónLa tecnología MOS es la base para el diseño de circuitos digitales actualmente y el MOSFET (Metal-OxideSemi conductor Field-Effect Transistor) es el dispositivo semiconductor más utilizado y constituye el elemento es...

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The impact of sub monolayers of HfO/sub 2/ on the device performance of high-k based transistors [MOSFETs]

Cited by 42 publications

References 2 publications

$1/f$ Noise in Drain and Gate Current of MOSFETs With High-$k$ Gate Stacks

$1/f$ Noise in Drain and Gate Current of MOSFETs With High-$k$ Gate Stacks

Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility

Caracterización eléctrica de nano-MOSFETs en tecnología SOI

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