The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI

Variability-aware design of subthreshold devices

“…There are two MOS scaling theories: Constant Electric (CE) field scaling [19] and Constant Voltage (CV) scaling [18]. In CE scaling, it has been proposed that for keep the short channel effect under control, the horizontal and vertical dimensions should be scaled down.…”

“…The CV theory retains the same scaling down theory as the CE, but the power supply voltage remains unchanged. Therefore, to maintain the charge-field, the doping densities are increased by a factor of S 2 [18]. However, the CV scaling inherently leads to a continuous increase of the transistor's internal electric field, which can cause reliability problems such as electron migration, hot carrier degradation, and oxide breakdown in recent CMOS process generations.…”

Verify and Extend VLSI Device Models

“…35 Um have not produced any evidence of ballistic transport. An interesting phenomenun associated with potential barriers at the source-channel and drain-channel junctions was observed.…”

“…In addition, with smaller probability of hole impact ionization at the drain end, 35 it may not be necessary to have a lightly doped region. Therefore, no distinction has been made in our analysis between shallow and deep source/drain regions for a p-channel device.…”

“…We have examined L -0. 35 jsm MOSFETs produced by vertical etch technique" between 18" and 300"K with no evidence of ballistic transport.…”