The impact of clock gating schemes on the power dissipation of synthesizable register files

Mueller, M.; Wortmann, Andreas; Simon, Sven; Kugel, M.; Schoenauer, T.

doi:10.1109/iscas.2004.1329345

Cited by 16 publications

(5 citation statements)

References 6 publications

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“…By clock gating, sub-modules are only active when they are needed and saving about 50% power consumption [23]. For example, the pie_decoder module only works in the RX stage, in PROCESS and TX stage, it sleeps.…”

Section: Clock Management and Clock Gatingmentioning

confidence: 99%

Implementation of a New RFID Authentication Protocol for EPC Gen2 Standard

Liu

et al. 2015

IEEE Sensors J.

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Researchers have revealed that electronic product code (EPC) Gen2 standard, which is designed for passive ultrahigh-frequency radio frequency identification has various security problems. To solve these problems, some authors have proposed many lightweight protocols to enhance security. However, it is still unclear about the feasibility of such protocols, since the hardware implementation of such protocols has long been neglected. Besides, it is extremely challengeable to achieve the balance among security, low power, and low cost. In this paper, a new lightweight mutual authentication protocol based on variable linear feedback shift registers is proposed, and its security analysis is described. An ASIC implementation of the new protocol compliant with the EPC Gen2 standard is presented as well. Several low-power techniques are used to obtain the goal of low-power consumption. The implementation result shows that the area of the baseband is 0.16 mm 2 and power consumption is 5.5 µW. As far as we know, this is the first ASIC implementation of a lightweight protocol compliant to EPC Gen2 standard. We believe that this design will bring a novel insight to future implementations for EPC Gen2v2 standard, which is ratified recently.

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Section: Clock Management and Clock Gatingmentioning

confidence: 99%

Implementation of a New RFID Authentication Protocol for EPC Gen2 Standard

Liu

et al. 2015

IEEE Sensors J.

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“…The former is a well-known approach which builds on the idea of disabling blocks when they are dispensable, thus reducing the overall power consumption of the system [18], [19]. For instance, if the processor has not completely interpreted a received command, there is no need to activate those blocks involved in the backward link communication.…”

Section: Timing Unitmentioning

confidence: 99%

An Ultralow-Power Mixed-Signal Back End for Passive Sensor UHF RFID Transponders

Rodríguez-Rodríguez

Delgado‐Restituto

Masuch

et al. 2012

IEEE Trans. Ind. Electron.

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This paper describes the design of mixed-signal back end for an ultrahigh-frequency sensor-enabled radio-frequency identification transponder in full compliance with the Electronic Product Code Class-1 Generation-2 protocol, defined in the standard ISO 18000-6C. The chip, implemented in a low-cost 0.35-µm CMOS technology process, includes a baseband processor, an analog-to-digital converter (ADC) to digitize the signal acquired from the external sensor, and some auxiliary circuitry for voltage regulation and reference generation. The proposed solution uses two different supply voltages, one for the processor and the other for the mixed-signal circuitry, and defines a novel communication protocol between both blocks so that analog readouts are minimally affected by the digital activity of the tag. The whole system was first functionally validated by exhaustively testing with external dc power supplies ten prototype samples, and then, the two main blocks, processor, and ADC were individually tested to assess their performance limits. Regarding the baseband processor, experiments were performed toward the calculation of its packet error rate (PER) under two typical biasing configurations of passive tags, using either crude clamps or regulators. It was found that the regulated biasing outperforms the clamping solution and obtains a PER of 3 × 10 −3 with a supply voltage of 0.75 V. The current consumption of the processor during the reception and response to a Read command at maximum backward rate is only 2.2 µA from a 0.9-V supply. Regarding the ADC, it is a 10-b successive approximation register converter which obtains 9.41 b of effective resolution at 2-kS/s sampling frequency with a power consumption of 250 nW, including the dissipation of a current generation cell and the clock generation circuitry, from 1-V supply.

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“…In CMOS circuits, the dynamic power consumption caused by propagations and transitions of clock signals consumes a large amount of energy in the system, and clock gating is a simple and effective method for decreasing dynamic power consumption [17,18] . In this paper, dynamic clock gating (DCG) technology based on finite state machine (FSM) and clock gating (CG) is adopted.…”

Section: Power Management Strategymentioning

confidence: 99%

Novel frequency hopping sequences generator based on AES algorithm

Zhang

Zhou

et al. 2010

Trans. Tianjin Univ.

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Abstract：A novel frequency hopping (FH) sequences generator based on advanced encryption standard (AES) iterated block cipher is proposed for FH communication systems. The analysis shows that the FH sequences based on AES algorithm have good performance in uniformity, correlation, complexity and security. A high-speed, low-power and low-cost ASIC of FH sequences generator is implemented by optimizing the structure of S-Box and MixColumns of AES algorithm, proposing a hierarchical power management strategy, and applying the dynamic clock gating technology based on finite state machine and clock gating. SMIC 0.18 μm standard CMOS technology shows that the scale of ASIC is only about 10.68 kgate, power consumption is 33.8 μW/MHz, and the maximum hop-rate is 1 098 901 hop/s. This design is suitable for portable FH communication system for its advantages in high-security and hop-rate, low-power and low-cost. The proposed FH sequences generator has been employed in Bluetooth SoC design. Keywords：frequency hopping sequences; advanced encryption standard; low-power; low-cost; application specific integrated circuit Recently, frequency hopping (FH) spread spectrum systems have become increasingly popular in military radio communication, mobile communication, modern radar and sonar echolocation systems for their excellent anti-jamming and multiple access properties [1] . Families of FH sequences, which are used to specify the transmission frequency at a given time, play an important role in FH communications. For Bluetooth network communication, the performance in security and antijamming based on the original FH sequences constructed by papilionaceous algorithm cannot satisfy the requirements of communication, especially in military fields. Although some FH sequences based on block ciphers were proposed for Bluetooth in Refs. [2, 3], the higher requirements for security, power consumption and cost were not discussed in detail. As we know, the higher performance means the increase of complexity and cost, so designing an FH sequences generator with good performance not only in uniformity, correlation, complexity and security, but also in hop-rate, power consumption and cost is a big challenge. In this paper, the performance of FH pattern based on the advanced encryption standard (AES) block cipher mechanism is analyzed, and then a high hop-rate, low-power and lowcost ASIC of the FH sequences generator is implemented.

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The impact of clock gating schemes on the power dissipation of synthesizable register files

Cited by 16 publications

References 6 publications

Implementation of a New RFID Authentication Protocol for EPC Gen2 Standard

Implementation of a New RFID Authentication Protocol for EPC Gen2 Standard

An Ultralow-Power Mixed-Signal Back End for Passive Sensor UHF RFID Transponders

Novel frequency hopping sequences generator based on AES algorithm

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